Searched refs:FSL_CORENET2_RCWSR4_SRDS1_PRTCL (Results 1 – 15 of 15) sorted by relevance
50 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in checkboard()102 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_mux_lane()
39 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_eth_init()
38 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_eth_init()
131 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in serdes_get_first_lane()354 FSL_CORENET2_RCWSR4_SRDS1_PRTCL, in fsl_serdes_init()
239 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in initialize_lane_to_slot()263 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_eth_init()
96 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_mux_lane_to_slot()
213 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_ft_fman_fixup_port()452 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in initialize_lane_to_slot()525 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_eth_init()
100 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in brd_mux_lane_to_slot()
49 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_eth_init()
161 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_eth_init()
340 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in configure_vsc3316_3308()784 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in config_serdes1_refclks()
191 FSL_CORENET2_RCWSR4_SRDS1_PRTCL) in initialize_lane_to_slot()
1763 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 macro1773 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 macro1779 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 macro1799 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 macro1813 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 macro
353 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in config_frontside_crossbar_vsc3316()
497 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in board_eth_init()