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Searched refs:CTRL_BASE (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dhardware_ti814x.h23 #define CTRL_BASE 0x48140000 macro
48 #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
H A Dhardware_am33xx.h26 #define CTRL_BASE 0x44E10000 macro
51 #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
H A Dmux_ti814x.h29 tmp = __raw_readl(CTRL_BASE + offset); \
31 __raw_writel(tmp | value, (CTRL_BASE + offset));\
H A Dhardware_ti816x.h33 #define CTRL_BASE 0x48140000 macro
H A Dhardware_am43xx.h29 #define CTRL_BASE 0x44E10000 macro
H A Dmux_am43xx.h16 __raw_writel(value, (CTRL_BASE + offset));
H A Dmux_am33xx.h23 __raw_writel(value, (CTRL_BASE + offset));
H A Dmux_ti816x.h24 __raw_writel(value, (CTRL_BASE + offset));
H A Dcpu.h44 #define DEVICE_ID (CTRL_BASE + 0x0600)
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/am33xx/
H A Dsys_info.c23 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
63 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; in get_sys_clk_index()
H A Dclock_ti816x.c33 #define CM_PLL_BASE (CTRL_BASE + 0x0400)
73 #define CONTROL_STATUS (CTRL_BASE + 0x40)
74 #define DDR_RCD (CTRL_BASE + 0x070C)
H A Dprcm-regs.c14 .control_status = CTRL_BASE + 0x40,
H A Dclock_ti814x.c105 #define SATA_PLL_BASE (CTRL_BASE + 0x0720)
/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp/
H A Dregs_v2x.h9 #define CTRL_BASE 0x00000000 macro
10 #define CTRL_VI_ISP_EN (CTRL_BASE + 0x00000)
11 #define CTRL_VI_ISP_PATH (CTRL_BASE + 0x00004)
12 #define CTRL_VI_ID (CTRL_BASE + 0x00008)
13 #define CTRL_VI_ISP_CLK_CTRL (CTRL_BASE + 0x0000c)
14 #define CTRL_VI_ICCL (CTRL_BASE + 0x00010)
15 #define CTRL_VI_IRCL (CTRL_BASE + 0x00014)
16 #define CTRL_VI_DPCL (CTRL_BASE + 0x00018)
17 #define CTRL_SWS_CFG (CTRL_BASE + 0x0001c)
18 #define LVDS_CTRL (CTRL_BASE + 0x00020)
[all …]
/OK3568_Linux_fs/u-boot/board/ti/am43xx/
H A Dboard.c348 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; in get_opp_offset()