1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * hardware_am43xx.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * AM43xx hardware specific header 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __AM43XX_HARDWARE_AM43XX_H 12*4882a593Smuzhiyun #define __AM43XX_HARDWARE_AM43XX_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Module base addresses */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* L3 Fast Configuration Bandwidth Limiter Base Address */ 17*4882a593Smuzhiyun #define L3F_CFG_BWLIMITER 0x44005200 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* UART Base Address */ 20*4882a593Smuzhiyun #define UART0_BASE 0x44E09000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* GPIO Base address */ 23*4882a593Smuzhiyun #define GPIO2_BASE 0x481AC000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Watchdog Timer */ 26*4882a593Smuzhiyun #define WDT_BASE 0x44E35000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Control Module Base Address */ 29*4882a593Smuzhiyun #define CTRL_BASE 0x44E10000 30*4882a593Smuzhiyun #define CTRL_DEVICE_BASE 0x44E10600 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* PRCM Base Address */ 33*4882a593Smuzhiyun #define PRCM_BASE 0x44DF0000 34*4882a593Smuzhiyun #define CM_WKUP 0x44DF2800 35*4882a593Smuzhiyun #define CM_PER 0x44DF8800 36*4882a593Smuzhiyun #define CM_DPLL 0x44DF4200 37*4882a593Smuzhiyun #define CM_RTC 0x44DF8500 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PRM_RSTCTRL (PRCM_BASE + 0x4000) 40*4882a593Smuzhiyun #define PRM_RSTST (PRM_RSTCTRL + 4) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* VTP Base address */ 43*4882a593Smuzhiyun #define VTP0_CTRL_ADDR 0x44E10E0C 44*4882a593Smuzhiyun #define VTP1_CTRL_ADDR 0x48140E10 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* USB CTRL Base Address */ 47*4882a593Smuzhiyun #define USB1_CTRL 0x44e10628 48*4882a593Smuzhiyun #define USB1_CTRL_CM_PWRDN BIT(0) 49*4882a593Smuzhiyun #define USB1_CTRL_OTG_PWRDN BIT(1) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* DDR Base address */ 52*4882a593Smuzhiyun #define DDR_PHY_CMD_ADDR 0x44E12000 53*4882a593Smuzhiyun #define DDR_PHY_DATA_ADDR 0x44E120C8 54*4882a593Smuzhiyun #define DDR_PHY_CMD_ADDR2 0x47C0C800 55*4882a593Smuzhiyun #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 56*4882a593Smuzhiyun #define DDR_DATA_REGS_NR 2 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* CPSW Config space */ 59*4882a593Smuzhiyun #define CPSW_MDIO_BASE 0x4A101000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* RTC base address */ 62*4882a593Smuzhiyun #define RTC_BASE 0x44E3E000 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* USB OTG */ 65*4882a593Smuzhiyun #define USB_OTG_SS1_BASE 0x48390000 66*4882a593Smuzhiyun #define USB_OTG_SS1_GLUE_BASE 0x48380000 67*4882a593Smuzhiyun #define USB2_PHY1_POWER 0x44E10620 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define USB_OTG_SS2_BASE 0x483D0000 70*4882a593Smuzhiyun #define USB_OTG_SS2_GLUE_BASE 0x483C0000 71*4882a593Smuzhiyun #define USB2_PHY2_POWER 0x44E10628 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* USB Clock Control */ 74*4882a593Smuzhiyun #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260) 75*4882a593Smuzhiyun #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268) 76*4882a593Smuzhiyun #define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1) 77*4882a593Smuzhiyun #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) 80*4882a593Smuzhiyun #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) 81*4882a593Smuzhiyun #define USBPHYOCPSCP_MODULE_EN (1 << 1) 82*4882a593Smuzhiyun #define CM_DEVICE_INST 0x44df4100 83*4882a593Smuzhiyun #define PRM_DEVICE_INST 0x44df4000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8) 86*4882a593Smuzhiyun #define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* EDMA3 Base Address */ 89*4882a593Smuzhiyun #define EDMA3_BASE 0x49000000 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* __AM43XX_HARDWARE_AM43XX_H */ 92