1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * hardware_ti816x.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * TI816x hardware specific header 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 7*4882a593Smuzhiyun * Antoine Tenart, <atenart@adeneo-embedded.com> 8*4882a593Smuzhiyun * Based on TI-PSP-04.00.02.14 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 11*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 12*4882a593Smuzhiyun * published by the Free Software Foundation; either version 2 of 13*4882a593Smuzhiyun * the License, or (at your option) any later version. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 16*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 18*4882a593Smuzhiyun * GNU General Public License for more details. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef __AM33XX_HARDWARE_TI816X_H 22*4882a593Smuzhiyun #define __AM33XX_HARDWARE_TI816X_H 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* UART */ 25*4882a593Smuzhiyun #define UART0_BASE 0x48020000 26*4882a593Smuzhiyun #define UART1_BASE 0x48022000 27*4882a593Smuzhiyun #define UART2_BASE 0x48024000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Watchdog Timer */ 30*4882a593Smuzhiyun #define WDT_BASE 0x480C2000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Control Module Base Address */ 33*4882a593Smuzhiyun #define CTRL_BASE 0x48140000 34*4882a593Smuzhiyun #define CTRL_DEVICE_BASE 0x48140600 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* PRCM Base Address */ 37*4882a593Smuzhiyun #define PRCM_BASE 0x48180000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PRM_RSTCTRL (PRCM_BASE + 0x00A0) 40*4882a593Smuzhiyun #define PRM_RSTST (PRM_RSTCTRL + 8) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* VTP Base address */ 43*4882a593Smuzhiyun #define VTP0_CTRL_ADDR 0x48198358 44*4882a593Smuzhiyun #define VTP1_CTRL_ADDR 0x4819A358 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* DDR Base address */ 47*4882a593Smuzhiyun #define DDR_PHY_CMD_ADDR 0x48198000 48*4882a593Smuzhiyun #define DDR_PHY_DATA_ADDR 0x481980C8 49*4882a593Smuzhiyun #define DDR_PHY_CMD_ADDR2 0x4819A000 50*4882a593Smuzhiyun #define DDR_PHY_DATA_ADDR2 0x4819A0C8 51*4882a593Smuzhiyun #define DDR_DATA_REGS_NR 4 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define DDRPHY_0_CONFIG_BASE 0x48198000 55*4882a593Smuzhiyun #define DDRPHY_1_CONFIG_BASE 0x4819A000 56*4882a593Smuzhiyun #define DDRPHY_CONFIG_BASE ((emif == 0) ? \ 57*4882a593Smuzhiyun DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* RTC base address */ 60*4882a593Smuzhiyun #define RTC_BASE 0x480C0000 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* __AM33XX_HARDWARE_TI816X_H */ 63