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Searched refs:CLK_OPS_PARENT_ENABLE (Results 1 – 11 of 11) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk.h302 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, in imx_clk_hw_divider2()
311 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, in imx_clk_divider2_flags()
377 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, in imx_clk_hw_gate2_shared2()
387 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, in imx_dev_clk_hw_gate_shared()
403 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, in imx_clk_hw_gate3()
412 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, in imx_clk_hw_gate3_flags()
423 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, in imx_clk_hw_gate4()
432 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, in imx_clk_hw_gate4_flags()
462 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, in imx_clk_mux2()
473 CLK_OPS_PARENT_ENABLE, in imx_clk_hw_mux2()
[all …]
H A Dclk-imx7d.c709 …root_clk", "ahb_root_clk", base + 0x9080, 0, 2, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE | CLK_SET_… in imx7d_clocks_init()
773 …= imx_clk_hw_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
775 …gs("main_axi_root_clk", "axi_post_div", base + 0x4040, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
780 …flags("dram_root_clk", "dram_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
781 …s("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
782 …lt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
783 …ram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE); in imx7d_clocks_init()
H A Dclk-imx8mq.c552 …_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); in imx8mq_clocks_probe()
554 …_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); in imx8mq_clocks_probe()
560 …lags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); in imx8mq_clocks_probe()
H A Dclk-imx7ulp.c108 …, base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); in imx7ulp_clk_scg1_init()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-stm32mp1.c1289 COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
1676 MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
1679 MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
1682 MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
1743 MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1746 MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1750 CLK_OPS_PARENT_ENABLE,
1756 CLK_OPS_PARENT_ENABLE,
1961 COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
1970 COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
[all …]
H A Dclk.c1255 if (core->flags & CLK_OPS_PARENT_ENABLE) in clk_disable_unused_subtree()
1287 if (core->flags & CLK_OPS_PARENT_ENABLE) in clk_disable_unused_subtree()
1859 if (core->flags & CLK_OPS_PARENT_ENABLE) { in __clk_set_parent_before()
1892 if (core->flags & CLK_OPS_PARENT_ENABLE) { in __clk_set_parent_after()
2178 if (core->flags & CLK_OPS_PARENT_ENABLE) in clk_change_rate()
2199 if (core->flags & CLK_OPS_PARENT_ENABLE) in clk_change_rate()
3212 ENTRY(CLK_OPS_PARENT_ENABLE),
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rv1126.c931 MUX(ACLK_PDVI, "aclk_pdvi", mux_aclk_pdvi_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
950 MUX(CLK_ISP, "clk_isp", mux_clk_isp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
998 MUX(ACLK_PDISPP, "aclk_pdispp", mux_aclk_pdispp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1014 MUX(CLK_ISPP, "clk_ispp", mux_clk_ispp_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1154 MUX(ACLK_PDNPU, "aclk_pdnpu", mux_aclk_pdnpu_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1172 MUX(CLK_CORE_NPU, "clk_core_npu", mux_clk_npu_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Dclk-rk1808.c341 COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
343 COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
H A Dclk-rk3568.c563 …_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dgpucc-msm8998.c141 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
/OK3568_Linux_fs/kernel/include/linux/
H A Dclk-provider.h32 #define CLK_OPS_PARENT_ENABLE BIT(12) macro