Searched refs:CAR (Results 1 – 25 of 28) sorted by relevance
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43 hex "Board specific Cache-As-RAM (CAR) address"46 This option specifies the board specific Cache-As-RAM (CAR) address.49 hex "Board specific Cache-As-RAM (CAR) size"52 This option specifies the board specific Cache-As-RAM (CAR) size.
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible11 - reg : Should contain CAR registers location and length16 CAR. The assignments may be found in header file19 In clock consumers, this cell represents the bit number in the CAR's
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible11 - reg : Should contain CAR registers location and length16 CAR. The assignments may be found in the header files21 In clock consumers, this cell represents the bit number in the CAR's
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible11 - reg : Should contain CAR registers location and length15 In clock consumers, this cell represents the clock ID exposed by the CAR.17 The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB18 registers. These IDs often match those in the CAR's RST_DEVICES registers,25 The balance of the clocks controlled by the CAR are assigned IDs of 96 and
2 bool "Enable Tegra CAR-based clock driver"6 register access to the Tegra CAR (Clock And Reset controller).
29 Space in bytes in eSRAM used as Cache-As-RAM (CAR).
7 CAR node and the clock number as a parameter:
72 #define CAR __REG(0x40500020) /* CODEC Access Register */ macro
44 bool "Enable Tegra CAR-based reset driver"48 direct register access to the Tegra CAR (Clock And Reset controller).
377 CAR is disabled.465 start address of the cache-as-RAM (CAR) area and the address varies466 depending on the CPU. Once CAR is set up, read/write memory becomes476 sets the size of the cache-as-RAM (CAR) area. Note that much of the477 CAR space is required by the MRC. The CAR space available to U-Boot485 This is the amount of CAR (Cache as RAM) reserved for use by the
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.107 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
132 Space in bytes in eSRAM used as Cache-As-ARM (CAR).
225 bool "Enable support for the Tegra CAR driver"228 The Tegra CAR (Clock and Reset Controller) is a HW module that
59 (0x01920000) Board specific Cache-As-RAM (CAR) address60 (0x4000) Board specific Cache-As-RAM (CAR) size63 to point to a new board. You can also change the Cache-As-RAM (CAR) related
412 #define CAR 0x40500020 /* CODEC Access Register */ macro
138 ARM RENESAS RMOBILE/R-CAR
899 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1712 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
13477 PCI DRIVER FOR RENESAS R-CAR14946 RENESAS R-CAR GYROADC DRIVER14953 RENESAS R-CAR I2C DRIVERS14961 RENESAS R-CAR THERMAL DRIVERS
3590 <S26CD> % DISABLED CAR3593 <S26D0> % CAR SLIDING6057 <S1F3CE> % RACING CAR6832 <S1F683> % RAILWAY CAR6840 <S1F68B> % TRAM CAR6848 <S1F693> % POLICE CAR6849 <S1F694> % ONCOMING POLICE CAR18148 <S10542> % CAUCASIAN ALBANIAN LETTER CAR57197 <U26CD> IGNORE;IGNORE;IGNORE;<U26CD> % DISABLED CAR57200 <U26D0> IGNORE;IGNORE;IGNORE;<U26D0> % CAR SLIDING[all …]
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