xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunNVIDIA Tegra124 and Tegra132 Clock And Reset Controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThis binding uses the common clock binding:
4*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunThe CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7*4882a593Smuzhiyunfor muxing and gating Tegra's clocks, and setting their rates.
8*4882a593Smuzhiyun
9*4882a593SmuzhiyunRequired properties :
10*4882a593Smuzhiyun- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11*4882a593Smuzhiyun- reg : Should contain CAR registers location and length
12*4882a593Smuzhiyun- clocks : Should contain phandle and clock specifiers for two clocks:
13*4882a593Smuzhiyun  the 32 KHz "32k_in", and the board-specific oscillator "osc".
14*4882a593Smuzhiyun- #clock-cells : Should be 1.
15*4882a593Smuzhiyun  In clock consumers, this cell represents the clock ID exposed by the
16*4882a593Smuzhiyun  CAR. The assignments may be found in the header files
17*4882a593Smuzhiyun  <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18*4882a593Smuzhiyun  to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19*4882a593Smuzhiyun  (for Tegra124-specific clocks).
20*4882a593Smuzhiyun- #reset-cells : Should be 1.
21*4882a593Smuzhiyun  In clock consumers, this cell represents the bit number in the CAR's
22*4882a593Smuzhiyun  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
23*4882a593Smuzhiyun- nvidia,external-memory-controller : phandle of the EMC driver.
24*4882a593Smuzhiyun
25*4882a593SmuzhiyunThe node should contain a "emc-timings" subnode for each supported RAM type (see
26*4882a593Smuzhiyunfield RAM_CODE in register PMC_STRAPPING_OPT_A).
27*4882a593Smuzhiyun
28*4882a593SmuzhiyunRequired properties for "emc-timings" nodes :
29*4882a593Smuzhiyun- nvidia,ram-code : Should contain the value of RAM_CODE this timing set
30*4882a593Smuzhiyun  is used for.
31*4882a593Smuzhiyun
32*4882a593SmuzhiyunEach "emc-timings" node should contain a "timing" subnode for every supported
33*4882a593SmuzhiyunEMC clock rate.
34*4882a593Smuzhiyun
35*4882a593SmuzhiyunRequired properties for "timing" nodes :
36*4882a593Smuzhiyun- clock-frequency : Should contain the memory clock rate to which this timing
37*4882a593Smuzhiyunrelates.
38*4882a593Smuzhiyun- nvidia,parent-clock-frequency : Should contain the rate at which the current
39*4882a593Smuzhiyunparent of the EMC clock should be running at this timing.
40*4882a593Smuzhiyun- clocks : Must contain an entry for each entry in clock-names.
41*4882a593Smuzhiyun  See ../clocks/clock-bindings.txt for details.
42*4882a593Smuzhiyun- clock-names : Must include the following entries:
43*4882a593Smuzhiyun  - emc-parent : the clock that should be the parent of the EMC clock at this
44*4882a593Smuzhiyuntiming.
45*4882a593Smuzhiyun
46*4882a593SmuzhiyunExample SoC include file:
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun/ {
49*4882a593Smuzhiyun	tegra_car: clock@60006000 {
50*4882a593Smuzhiyun		compatible = "nvidia,tegra124-car";
51*4882a593Smuzhiyun		reg = <0x60006000 0x1000>;
52*4882a593Smuzhiyun		#clock-cells = <1>;
53*4882a593Smuzhiyun		#reset-cells = <1>;
54*4882a593Smuzhiyun		nvidia,external-memory-controller = <&emc>;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	usb@c5004000 {
58*4882a593Smuzhiyun		clocks = <&tegra_car TEGRA124_CLK_USB2>;
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593SmuzhiyunExample board file:
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun/ {
65*4882a593Smuzhiyun	clocks {
66*4882a593Smuzhiyun		compatible = "simple-bus";
67*4882a593Smuzhiyun		#address-cells = <1>;
68*4882a593Smuzhiyun		#size-cells = <0>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		osc: clock@0 {
71*4882a593Smuzhiyun			compatible = "fixed-clock";
72*4882a593Smuzhiyun			reg = <0>;
73*4882a593Smuzhiyun			#clock-cells = <0>;
74*4882a593Smuzhiyun			clock-frequency = <112400000>;
75*4882a593Smuzhiyun		};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		clk_32k: clock@1 {
78*4882a593Smuzhiyun			compatible = "fixed-clock";
79*4882a593Smuzhiyun			reg = <1>;
80*4882a593Smuzhiyun			#clock-cells = <0>;
81*4882a593Smuzhiyun			clock-frequency = <32768>;
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	&tegra_car {
86*4882a593Smuzhiyun		clocks = <&clk_32k> <&osc>;
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	clock@60006000 {
90*4882a593Smuzhiyun		emc-timings-3 {
91*4882a593Smuzhiyun			nvidia,ram-code = <3>;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun			timing-12750000 {
94*4882a593Smuzhiyun				clock-frequency = <12750000>;
95*4882a593Smuzhiyun				nvidia,parent-clock-frequency = <408000000>;
96*4882a593Smuzhiyun				clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
97*4882a593Smuzhiyun				clock-names = "emc-parent";
98*4882a593Smuzhiyun			};
99*4882a593Smuzhiyun			timing-20400000 {
100*4882a593Smuzhiyun				clock-frequency = <20400000>;
101*4882a593Smuzhiyun				nvidia,parent-clock-frequency = <408000000>;
102*4882a593Smuzhiyun				clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
103*4882a593Smuzhiyun				clock-names = "emc-parent";
104*4882a593Smuzhiyun			};
105*4882a593Smuzhiyun		};
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun};
108