xref: /OK3568_Linux_fs/u-boot/drivers/misc/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun#
2*4882a593Smuzhiyun# Multifunction miscellaneous devices
3*4882a593Smuzhiyun#
4*4882a593Smuzhiyun
5*4882a593Smuzhiyunmenu "Multifunction device drivers"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyunconfig MISC
8*4882a593Smuzhiyun	bool "Enable Driver Model for Misc drivers"
9*4882a593Smuzhiyun	depends on DM
10*4882a593Smuzhiyun	help
11*4882a593Smuzhiyun	  Enable driver model for miscellaneous devices. This class is
12*4882a593Smuzhiyun	  used only for those do not fit other more general classes. A
13*4882a593Smuzhiyun	  set of generic read, write and ioctl methods may be used to
14*4882a593Smuzhiyun	  access the device.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunconfig SPL_MISC
17*4882a593Smuzhiyun	bool "Enable Driver Model for Misc drivers in SPL"
18*4882a593Smuzhiyun	depends on SPL_DM
19*4882a593Smuzhiyun	help
20*4882a593Smuzhiyun	  Enable driver model for miscellaneous devices. This class is
21*4882a593Smuzhiyun	  used only for those do not fit other more general classes. A
22*4882a593Smuzhiyun	  set of generic read, write and ioctl methods may be used to
23*4882a593Smuzhiyun	  access the device.
24*4882a593Smuzhiyun
25*4882a593Smuzhiyunconfig TPL_MISC
26*4882a593Smuzhiyun	bool "Enable Driver Model for Misc drivers in TPL"
27*4882a593Smuzhiyun	depends on TPL_DM
28*4882a593Smuzhiyun	help
29*4882a593Smuzhiyun	  Enable driver model for miscellaneous devices. This class is
30*4882a593Smuzhiyun	  used only for those do not fit other more general classes. A
31*4882a593Smuzhiyun	  set of generic read, write and ioctl methods may be used to
32*4882a593Smuzhiyun	  access the device.
33*4882a593Smuzhiyun
34*4882a593Smuzhiyunconfig MISC_DECOMPRESS
35*4882a593Smuzhiyun	bool "Enable misc decompress driver support"
36*4882a593Smuzhiyun	depends on MISC
37*4882a593Smuzhiyun	help
38*4882a593Smuzhiyun	  Enable misc decompress driver support.
39*4882a593Smuzhiyun
40*4882a593Smuzhiyunconfig SPL_MISC_DECOMPRESS
41*4882a593Smuzhiyun	bool "Enable misc decompress driver support in SPL"
42*4882a593Smuzhiyun	depends on SPL_MISC
43*4882a593Smuzhiyun	help
44*4882a593Smuzhiyun	  Enable misc decompress driver support in spl.
45*4882a593Smuzhiyun
46*4882a593Smuzhiyunconfig ALTERA_SYSID
47*4882a593Smuzhiyun	bool "Altera Sysid support"
48*4882a593Smuzhiyun	depends on MISC
49*4882a593Smuzhiyun	help
50*4882a593Smuzhiyun	  Select this to enable a sysid for Altera devices. Please find
51*4882a593Smuzhiyun	  details on the "Embedded Peripherals IP User Guide" of Altera.
52*4882a593Smuzhiyun
53*4882a593Smuzhiyunconfig ATSHA204A
54*4882a593Smuzhiyun	bool "Support for Atmel ATSHA204A module"
55*4882a593Smuzhiyun	depends on MISC
56*4882a593Smuzhiyun	help
57*4882a593Smuzhiyun	   Enable support for I2C connected Atmel's ATSHA204A
58*4882a593Smuzhiyun	   CryptoAuthentication module found for example on the Turris Omnia
59*4882a593Smuzhiyun	   board.
60*4882a593Smuzhiyun
61*4882a593Smuzhiyunconfig ROCKCHIP_EFUSE
62*4882a593Smuzhiyun        bool "Rockchip e-fuse support"
63*4882a593Smuzhiyun	depends on MISC
64*4882a593Smuzhiyun	help
65*4882a593Smuzhiyun	  Enable (read-only) access for the e-fuse block found in Rockchip
66*4882a593Smuzhiyun	  SoCs: accesses can either be made using byte addressing and a length
67*4882a593Smuzhiyun	  or through child-nodes that are generated based on the e-fuse map
68*4882a593Smuzhiyun	  retrieved from the DTS.
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	  This driver currently supports the RK3399 only, but can easily be
71*4882a593Smuzhiyun	  extended (by porting the read function from the Linux kernel sources)
72*4882a593Smuzhiyun	  to support other recent Rockchip devices.
73*4882a593Smuzhiyun
74*4882a593Smuzhiyunconfig ROCKCHIP_OTP
75*4882a593Smuzhiyun	bool "Rockchip OTP Support"
76*4882a593Smuzhiyun	depends on MISC
77*4882a593Smuzhiyun	help
78*4882a593Smuzhiyun	  This is a simple drive to dump specified values of Rockchip SoC
79*4882a593Smuzhiyun	  from otp, such as cpu-leakage.
80*4882a593Smuzhiyun
81*4882a593Smuzhiyunconfig ROCKCHIP_HW_DECOMPRESS
82*4882a593Smuzhiyun	bool "Rockchip HardWare Decompress Support"
83*4882a593Smuzhiyun	depends on MISC_DECOMPRESS
84*4882a593Smuzhiyun	help
85*4882a593Smuzhiyun	  This driver support Decompress IP built-in Rockchip SoC, support
86*4882a593Smuzhiyun	  LZ4, GZIP, PNG, ZLIB.
87*4882a593Smuzhiyun
88*4882a593Smuzhiyunconfig SPL_ROCKCHIP_HW_DECOMPRESS
89*4882a593Smuzhiyun	bool "Rockchip HardWare Decompress Support"
90*4882a593Smuzhiyun	depends on SPL_MISC_DECOMPRESS
91*4882a593Smuzhiyun	help
92*4882a593Smuzhiyun	  This driver support Decompress IP built-in Rockchip SoC, support
93*4882a593Smuzhiyun	  LZ4, GZIP, PNG, ZLIB.
94*4882a593Smuzhiyun
95*4882a593Smuzhiyunconfig ROCKCHIP_SECURE_OTP
96*4882a593Smuzhiyun	bool "Rockchip Secure OTP Support"
97*4882a593Smuzhiyun	depends on MISC && !OPTEE_CLIENT
98*4882a593Smuzhiyun	help
99*4882a593Smuzhiyun	  Support read & write secure otp.
100*4882a593Smuzhiyun
101*4882a593Smuzhiyunconfig SPL_ROCKCHIP_SECURE_OTP
102*4882a593Smuzhiyun	bool "Rockchip Secure OTP Support in spl"
103*4882a593Smuzhiyun	depends on SPL_MISC
104*4882a593Smuzhiyun	help
105*4882a593Smuzhiyun	  Support read & write secure otp in spl.
106*4882a593Smuzhiyun
107*4882a593Smuzhiyunconfig CMD_CROS_EC
108*4882a593Smuzhiyun	bool "Enable crosec command"
109*4882a593Smuzhiyun	depends on CROS_EC
110*4882a593Smuzhiyun	help
111*4882a593Smuzhiyun	  Enable command-line access to the Chrome OS EC (Embedded
112*4882a593Smuzhiyun	  Controller). This provides the 'crosec' command which has
113*4882a593Smuzhiyun	  a number of sub-commands for performing EC tasks such as
114*4882a593Smuzhiyun	  updating its flash, accessing a small saved context area
115*4882a593Smuzhiyun	  and talking to the I2C bus behind the EC (if there is one).
116*4882a593Smuzhiyun
117*4882a593Smuzhiyunconfig CROS_EC
118*4882a593Smuzhiyun	bool "Enable Chrome OS EC"
119*4882a593Smuzhiyun	help
120*4882a593Smuzhiyun	  Enable access to the Chrome OS EC. This is a separate
121*4882a593Smuzhiyun	  microcontroller typically available on a SPI bus on Chromebooks. It
122*4882a593Smuzhiyun	  provides access to the keyboard, some internal storage and may
123*4882a593Smuzhiyun	  control access to the battery and main PMIC depending on the
124*4882a593Smuzhiyun	  device. You can use the 'crosec' command to access it.
125*4882a593Smuzhiyun
126*4882a593Smuzhiyunconfig CROS_EC_I2C
127*4882a593Smuzhiyun	bool "Enable Chrome OS EC I2C driver"
128*4882a593Smuzhiyun	depends on CROS_EC
129*4882a593Smuzhiyun	help
130*4882a593Smuzhiyun	  Enable I2C access to the Chrome OS EC. This is used on older
131*4882a593Smuzhiyun	  ARM Chromebooks such as snow and spring before the standard bus
132*4882a593Smuzhiyun	  changed to SPI. The EC will accept commands across the I2C using
133*4882a593Smuzhiyun	  a special message protocol, and provide responses.
134*4882a593Smuzhiyun
135*4882a593Smuzhiyunconfig CROS_EC_LPC
136*4882a593Smuzhiyun	bool "Enable Chrome OS EC LPC driver"
137*4882a593Smuzhiyun	depends on CROS_EC
138*4882a593Smuzhiyun	help
139*4882a593Smuzhiyun	  Enable I2C access to the Chrome OS EC. This is used on x86
140*4882a593Smuzhiyun	  Chromebooks such as link and falco. The keyboard is provided
141*4882a593Smuzhiyun	  through a legacy port interface, so on x86 machines the main
142*4882a593Smuzhiyun	  function of the EC is power and thermal management.
143*4882a593Smuzhiyun
144*4882a593Smuzhiyunconfig CROS_EC_SANDBOX
145*4882a593Smuzhiyun	bool "Enable Chrome OS EC sandbox driver"
146*4882a593Smuzhiyun	depends on CROS_EC && SANDBOX
147*4882a593Smuzhiyun	help
148*4882a593Smuzhiyun	  Enable a sandbox emulation of the Chrome OS EC. This supports
149*4882a593Smuzhiyun	  keyboard (use the -l flag to enable the LCD), verified boot context,
150*4882a593Smuzhiyun	  EC flash read/write/erase support and a few other things. It is
151*4882a593Smuzhiyun	  enough to perform a Chrome OS verified boot on sandbox.
152*4882a593Smuzhiyun
153*4882a593Smuzhiyunconfig CROS_EC_SPI
154*4882a593Smuzhiyun	bool "Enable Chrome OS EC SPI driver"
155*4882a593Smuzhiyun	depends on CROS_EC
156*4882a593Smuzhiyun	help
157*4882a593Smuzhiyun	  Enable SPI access to the Chrome OS EC. This is used on newer
158*4882a593Smuzhiyun	  ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
159*4882a593Smuzhiyun	  provides a faster and more robust interface than I2C but the bugs
160*4882a593Smuzhiyun	  are less interesting.
161*4882a593Smuzhiyun
162*4882a593Smuzhiyunconfig DS4510
163*4882a593Smuzhiyun	bool "Enable support for DS4510 CPU supervisor"
164*4882a593Smuzhiyun	help
165*4882a593Smuzhiyun	  Enable support for the Maxim DS4510 CPU supervisor. It has an
166*4882a593Smuzhiyun	  integrated 64-byte EEPROM, four programmable non-volatile I/O pins
167*4882a593Smuzhiyun	  and a configurable timer for the supervisor function. The device is
168*4882a593Smuzhiyun	  connected over I2C.
169*4882a593Smuzhiyun
170*4882a593Smuzhiyunconfig FSL_SEC_MON
171*4882a593Smuzhiyun	bool "Enable FSL SEC_MON Driver"
172*4882a593Smuzhiyun	help
173*4882a593Smuzhiyun	  Freescale Security Monitor block is responsible for monitoring
174*4882a593Smuzhiyun	  system states.
175*4882a593Smuzhiyun	  Security Monitor can be transitioned on any security failures,
176*4882a593Smuzhiyun	  like software violations or hardware security violations.
177*4882a593Smuzhiyun
178*4882a593Smuzhiyunconfig MXC_OCOTP
179*4882a593Smuzhiyun	bool "Enable MXC OCOTP Driver"
180*4882a593Smuzhiyun	help
181*4882a593Smuzhiyun	  If you say Y here, you will get support for the One Time
182*4882a593Smuzhiyun	  Programmable memory pages that are stored on the some
183*4882a593Smuzhiyun	  Freescale i.MX processors.
184*4882a593Smuzhiyun
185*4882a593Smuzhiyunconfig NUVOTON_NCT6102D
186*4882a593Smuzhiyun	bool "Enable Nuvoton NCT6102D Super I/O driver"
187*4882a593Smuzhiyun	help
188*4882a593Smuzhiyun	  If you say Y here, you will get support for the Nuvoton
189*4882a593Smuzhiyun	  NCT6102D Super I/O driver. This can be used to enable or
190*4882a593Smuzhiyun	  disable the legacy UART, the watchdog or other devices
191*4882a593Smuzhiyun	  in the Nuvoton Super IO chips on X86 platforms.
192*4882a593Smuzhiyun
193*4882a593Smuzhiyunconfig PWRSEQ
194*4882a593Smuzhiyun	bool "Enable power-sequencing drivers"
195*4882a593Smuzhiyun	depends on DM
196*4882a593Smuzhiyun	help
197*4882a593Smuzhiyun	  Power-sequencing drivers provide support for controlling power for
198*4882a593Smuzhiyun	  devices. They are typically referenced by a phandle from another
199*4882a593Smuzhiyun	  device. When the device is started up, its power sequence can be
200*4882a593Smuzhiyun	  initiated.
201*4882a593Smuzhiyun
202*4882a593Smuzhiyunconfig SPL_PWRSEQ
203*4882a593Smuzhiyun	bool "Enable power-sequencing drivers for SPL"
204*4882a593Smuzhiyun	depends on PWRSEQ
205*4882a593Smuzhiyun	help
206*4882a593Smuzhiyun	  Power-sequencing drivers provide support for controlling power for
207*4882a593Smuzhiyun	  devices. They are typically referenced by a phandle from another
208*4882a593Smuzhiyun	  device. When the device is started up, its power sequence can be
209*4882a593Smuzhiyun	  initiated.
210*4882a593Smuzhiyun
211*4882a593Smuzhiyunconfig PCA9551_LED
212*4882a593Smuzhiyun	bool "Enable PCA9551 LED driver"
213*4882a593Smuzhiyun	help
214*4882a593Smuzhiyun	  Enable driver for PCA9551 LED controller. This controller
215*4882a593Smuzhiyun	  is connected via I2C. So I2C needs to be enabled.
216*4882a593Smuzhiyun
217*4882a593Smuzhiyunconfig PCA9551_I2C_ADDR
218*4882a593Smuzhiyun	hex "I2C address of PCA9551 LED controller"
219*4882a593Smuzhiyun	depends on PCA9551_LED
220*4882a593Smuzhiyun	default 0x60
221*4882a593Smuzhiyun	help
222*4882a593Smuzhiyun	  The I2C address of the PCA9551 LED controller.
223*4882a593Smuzhiyun
224*4882a593Smuzhiyunconfig TEGRA_CAR
225*4882a593Smuzhiyun	bool "Enable support for the Tegra CAR driver"
226*4882a593Smuzhiyun	depends on TEGRA_NO_BPMP
227*4882a593Smuzhiyun	help
228*4882a593Smuzhiyun	  The Tegra CAR (Clock and Reset Controller) is a HW module that
229*4882a593Smuzhiyun	  controls almost all clocks and resets in a Tegra SoC.
230*4882a593Smuzhiyun
231*4882a593Smuzhiyunconfig TEGRA186_BPMP
232*4882a593Smuzhiyun	bool "Enable support for the Tegra186 BPMP driver"
233*4882a593Smuzhiyun	depends on TEGRA186
234*4882a593Smuzhiyun	help
235*4882a593Smuzhiyun	  The Tegra BPMP (Boot and Power Management Processor) is a separate
236*4882a593Smuzhiyun	  auxiliary CPU embedded into Tegra to perform power management work,
237*4882a593Smuzhiyun	  and controls related features such as clocks, resets, power domains,
238*4882a593Smuzhiyun	  PMIC I2C bus, etc. This driver provides the core low-level
239*4882a593Smuzhiyun	  communication path by which feature-specific drivers (such as clock)
240*4882a593Smuzhiyun	  can make requests to the BPMP. This driver is similar to an MFD
241*4882a593Smuzhiyun	  driver in the Linux kernel.
242*4882a593Smuzhiyun
243*4882a593Smuzhiyunconfig WINBOND_W83627
244*4882a593Smuzhiyun	bool "Enable Winbond Super I/O driver"
245*4882a593Smuzhiyun	help
246*4882a593Smuzhiyun	  If you say Y here, you will get support for the Winbond
247*4882a593Smuzhiyun	  W83627 Super I/O driver. This can be used to enable the
248*4882a593Smuzhiyun	  legacy UART or other devices in the Winbond Super IO chips
249*4882a593Smuzhiyun	  on X86 platforms.
250*4882a593Smuzhiyun
251*4882a593Smuzhiyunconfig QFW
252*4882a593Smuzhiyun	bool
253*4882a593Smuzhiyun	help
254*4882a593Smuzhiyun	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
255*4882a593Smuzhiyun	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
256*4882a593Smuzhiyun
257*4882a593Smuzhiyunconfig I2C_EEPROM
258*4882a593Smuzhiyun	bool "Enable driver for generic I2C-attached EEPROMs"
259*4882a593Smuzhiyun	depends on MISC
260*4882a593Smuzhiyun	help
261*4882a593Smuzhiyun	  Enable a generic driver for EEPROMs attached via I2C.
262*4882a593Smuzhiyun
263*4882a593Smuzhiyunif I2C_EEPROM
264*4882a593Smuzhiyun
265*4882a593Smuzhiyunconfig SYS_I2C_EEPROM_ADDR
266*4882a593Smuzhiyun	hex "Chip address of the EEPROM device"
267*4882a593Smuzhiyun	default 0
268*4882a593Smuzhiyun
269*4882a593Smuzhiyunconfig SYS_I2C_EEPROM_BUS
270*4882a593Smuzhiyun	int "I2C bus of the EEPROM device."
271*4882a593Smuzhiyun	default 0
272*4882a593Smuzhiyun
273*4882a593Smuzhiyunconfig SYS_EEPROM_SIZE
274*4882a593Smuzhiyun	int "Size in bytes of the EEPROM device"
275*4882a593Smuzhiyun	default 256
276*4882a593Smuzhiyun
277*4882a593Smuzhiyunconfig SYS_EEPROM_PAGE_WRITE_BITS
278*4882a593Smuzhiyun	int "Number of bits used to address bytes in a single page"
279*4882a593Smuzhiyun	default 0
280*4882a593Smuzhiyun	help
281*4882a593Smuzhiyun	  The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
282*4882a593Smuzhiyun	  A 64 byte page, for example would require six bits.
283*4882a593Smuzhiyun
284*4882a593Smuzhiyunconfig SYS_EEPROM_PAGE_WRITE_DELAY_MS
285*4882a593Smuzhiyun	int "Number of milliseconds to delay between page writes"
286*4882a593Smuzhiyun	default 0
287*4882a593Smuzhiyun
288*4882a593Smuzhiyunconfig SYS_I2C_EEPROM_ADDR_LEN
289*4882a593Smuzhiyun	int "Length in bytes of the EEPROM memory array address"
290*4882a593Smuzhiyun	default 1
291*4882a593Smuzhiyun	help
292*4882a593Smuzhiyun	  Note: This is NOT the chip address length!
293*4882a593Smuzhiyun
294*4882a593Smuzhiyunconfig SYS_I2C_EEPROM_ADDR_OVERFLOW
295*4882a593Smuzhiyun	hex "EEPROM Address Overflow"
296*4882a593Smuzhiyun	default 0
297*4882a593Smuzhiyun	help
298*4882a593Smuzhiyun	  EEPROM chips that implement "address overflow" are ones
299*4882a593Smuzhiyun	  like Catalyst 24WC04/08/16 which has 9/10/11 bits of
300*4882a593Smuzhiyun	  address and the extra bits end up in the "chip address" bit
301*4882a593Smuzhiyun	  slots. This makes a 24WC08 (1Kbyte) chip look like four 256
302*4882a593Smuzhiyun	  byte chips.
303*4882a593Smuzhiyun
304*4882a593Smuzhiyunendif
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun
307*4882a593Smuzhiyunendmenu
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