1*4882a593SmuzhiyunNVIDIA Tegra20 Clock And Reset Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding uses the common clock binding: 4*4882a593SmuzhiyunDocumentation/devicetree/bindings/clock/clock-bindings.txt 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe CAR (Clock And Reset) Controller on Tegra is the HW module responsible 7*4882a593Smuzhiyunfor muxing and gating Tegra's clocks, and setting their rates. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties : 10*4882a593Smuzhiyun- compatible : Should be "nvidia,tegra20-car" 11*4882a593Smuzhiyun- reg : Should contain CAR registers location and length 12*4882a593Smuzhiyun- clocks : Should contain phandle and clock specifiers for two clocks: 13*4882a593Smuzhiyun the 32 KHz "32k_in", and the board-specific oscillator "osc". 14*4882a593Smuzhiyun- #clock-cells : Should be 1. 15*4882a593Smuzhiyun In clock consumers, this cell represents the clock ID exposed by the CAR. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 18*4882a593Smuzhiyun registers. These IDs often match those in the CAR's RST_DEVICES registers, 19*4882a593Smuzhiyun but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 20*4882a593Smuzhiyun this case, those clocks are assigned IDs above 95 in order to highlight 21*4882a593Smuzhiyun this issue. Implementations that interpret these clock IDs as bit values 22*4882a593Smuzhiyun within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 23*4882a593Smuzhiyun explicitly handle these special cases. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun The balance of the clocks controlled by the CAR are assigned IDs of 96 and 26*4882a593Smuzhiyun above. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun 0 cpu 29*4882a593Smuzhiyun 1 unassigned 30*4882a593Smuzhiyun 2 unassigned 31*4882a593Smuzhiyun 3 ac97 32*4882a593Smuzhiyun 4 rtc 33*4882a593Smuzhiyun 5 tmr 34*4882a593Smuzhiyun 6 uart1 35*4882a593Smuzhiyun 7 unassigned (register bit affects uart2 and vfir) 36*4882a593Smuzhiyun 8 gpio 37*4882a593Smuzhiyun 9 sdmmc2 38*4882a593Smuzhiyun 10 unassigned (register bit affects spdif_in and spdif_out) 39*4882a593Smuzhiyun 11 i2s1 40*4882a593Smuzhiyun 12 i2c1 41*4882a593Smuzhiyun 13 ndflash 42*4882a593Smuzhiyun 14 sdmmc1 43*4882a593Smuzhiyun 15 sdmmc4 44*4882a593Smuzhiyun 16 twc 45*4882a593Smuzhiyun 17 pwm 46*4882a593Smuzhiyun 18 i2s2 47*4882a593Smuzhiyun 19 epp 48*4882a593Smuzhiyun 20 unassigned (register bit affects vi and vi_sensor) 49*4882a593Smuzhiyun 21 2d 50*4882a593Smuzhiyun 22 usbd 51*4882a593Smuzhiyun 23 isp 52*4882a593Smuzhiyun 24 3d 53*4882a593Smuzhiyun 25 ide 54*4882a593Smuzhiyun 26 disp2 55*4882a593Smuzhiyun 27 disp1 56*4882a593Smuzhiyun 28 host1x 57*4882a593Smuzhiyun 29 vcp 58*4882a593Smuzhiyun 30 unassigned 59*4882a593Smuzhiyun 31 cache2 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun 32 mem 62*4882a593Smuzhiyun 33 ahbdma 63*4882a593Smuzhiyun 34 apbdma 64*4882a593Smuzhiyun 35 unassigned 65*4882a593Smuzhiyun 36 kbc 66*4882a593Smuzhiyun 37 stat_mon 67*4882a593Smuzhiyun 38 pmc 68*4882a593Smuzhiyun 39 fuse 69*4882a593Smuzhiyun 40 kfuse 70*4882a593Smuzhiyun 41 sbc1 71*4882a593Smuzhiyun 42 snor 72*4882a593Smuzhiyun 43 spi1 73*4882a593Smuzhiyun 44 sbc2 74*4882a593Smuzhiyun 45 xio 75*4882a593Smuzhiyun 46 sbc3 76*4882a593Smuzhiyun 47 dvc 77*4882a593Smuzhiyun 48 dsi 78*4882a593Smuzhiyun 49 unassigned (register bit affects tvo and cve) 79*4882a593Smuzhiyun 50 mipi 80*4882a593Smuzhiyun 51 hdmi 81*4882a593Smuzhiyun 52 csi 82*4882a593Smuzhiyun 53 tvdac 83*4882a593Smuzhiyun 54 i2c2 84*4882a593Smuzhiyun 55 uart3 85*4882a593Smuzhiyun 56 unassigned 86*4882a593Smuzhiyun 57 emc 87*4882a593Smuzhiyun 58 usb2 88*4882a593Smuzhiyun 59 usb3 89*4882a593Smuzhiyun 60 mpe 90*4882a593Smuzhiyun 61 vde 91*4882a593Smuzhiyun 62 bsea 92*4882a593Smuzhiyun 63 bsev 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun 64 speedo 95*4882a593Smuzhiyun 65 uart4 96*4882a593Smuzhiyun 66 uart5 97*4882a593Smuzhiyun 67 i2c3 98*4882a593Smuzhiyun 68 sbc4 99*4882a593Smuzhiyun 69 sdmmc3 100*4882a593Smuzhiyun 70 pcie 101*4882a593Smuzhiyun 71 owr 102*4882a593Smuzhiyun 72 afi 103*4882a593Smuzhiyun 73 csite 104*4882a593Smuzhiyun 74 unassigned 105*4882a593Smuzhiyun 75 avpucq 106*4882a593Smuzhiyun 76 la 107*4882a593Smuzhiyun 77 unassigned 108*4882a593Smuzhiyun 78 unassigned 109*4882a593Smuzhiyun 79 unassigned 110*4882a593Smuzhiyun 80 unassigned 111*4882a593Smuzhiyun 81 unassigned 112*4882a593Smuzhiyun 82 unassigned 113*4882a593Smuzhiyun 83 unassigned 114*4882a593Smuzhiyun 84 irama 115*4882a593Smuzhiyun 85 iramb 116*4882a593Smuzhiyun 86 iramc 117*4882a593Smuzhiyun 87 iramd 118*4882a593Smuzhiyun 88 cram2 119*4882a593Smuzhiyun 89 audio_2x a/k/a audio_2x_sync_clk 120*4882a593Smuzhiyun 90 clk_d 121*4882a593Smuzhiyun 91 unassigned 122*4882a593Smuzhiyun 92 sus 123*4882a593Smuzhiyun 93 cdev1 124*4882a593Smuzhiyun 94 cdev2 125*4882a593Smuzhiyun 95 unassigned 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun 96 uart2 128*4882a593Smuzhiyun 97 vfir 129*4882a593Smuzhiyun 98 spdif_in 130*4882a593Smuzhiyun 99 spdif_out 131*4882a593Smuzhiyun 100 vi 132*4882a593Smuzhiyun 101 vi_sensor 133*4882a593Smuzhiyun 102 tvo 134*4882a593Smuzhiyun 103 cve 135*4882a593Smuzhiyun 104 osc 136*4882a593Smuzhiyun 105 clk_32k a/k/a clk_s 137*4882a593Smuzhiyun 106 clk_m 138*4882a593Smuzhiyun 107 sclk 139*4882a593Smuzhiyun 108 cclk 140*4882a593Smuzhiyun 109 hclk 141*4882a593Smuzhiyun 110 pclk 142*4882a593Smuzhiyun 111 blink 143*4882a593Smuzhiyun 112 pll_a 144*4882a593Smuzhiyun 113 pll_a_out0 145*4882a593Smuzhiyun 114 pll_c 146*4882a593Smuzhiyun 115 pll_c_out1 147*4882a593Smuzhiyun 116 pll_d 148*4882a593Smuzhiyun 117 pll_d_out0 149*4882a593Smuzhiyun 118 pll_e 150*4882a593Smuzhiyun 119 pll_m 151*4882a593Smuzhiyun 120 pll_m_out1 152*4882a593Smuzhiyun 121 pll_p 153*4882a593Smuzhiyun 122 pll_p_out1 154*4882a593Smuzhiyun 123 pll_p_out2 155*4882a593Smuzhiyun 124 pll_p_out3 156*4882a593Smuzhiyun 125 pll_p_out4 157*4882a593Smuzhiyun 126 pll_s 158*4882a593Smuzhiyun 127 pll_u 159*4882a593Smuzhiyun 128 pll_x 160*4882a593Smuzhiyun 129 cop a/k/a avp 161*4882a593Smuzhiyun 130 audio a/k/a audio_sync_clk 162*4882a593Smuzhiyun 163*4882a593SmuzhiyunExample SoC include file: 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun/ { 166*4882a593Smuzhiyun tegra_car: clock@60006000 { 167*4882a593Smuzhiyun compatible = "nvidia,tegra20-car"; 168*4882a593Smuzhiyun reg = <0x60006000 0x1000>; 169*4882a593Smuzhiyun #clock-cells = <1>; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun usb@c5004000 { 173*4882a593Smuzhiyun clocks = <&tegra_car 58>; /* usb2 */ 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593SmuzhiyunExample board file: 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun/ { 180*4882a593Smuzhiyun clocks { 181*4882a593Smuzhiyun #address-cells = <1>; 182*4882a593Smuzhiyun #size-cells = <0>; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun osc: clock { 185*4882a593Smuzhiyun compatible = "fixed-clock"; 186*4882a593Smuzhiyun #clock-cells = <0>; 187*4882a593Smuzhiyun clock-frequency = <12000000>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun i2c@7000d000 { 192*4882a593Smuzhiyun pmic@34 { 193*4882a593Smuzhiyun compatible = "ti,tps6586x"; 194*4882a593Smuzhiyun reg = <0x34>; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun clk_32k: clock { 197*4882a593Smuzhiyun compatible = "fixed-clock"; 198*4882a593Smuzhiyun #clock-cells = <0>; 199*4882a593Smuzhiyun clock-frequency = <32768>; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun &tegra_car { 205*4882a593Smuzhiyun clocks = <&clk_32k> <&osc>; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun}; 208