1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_ARCH_REGS_AC97_H 3*4882a593Smuzhiyun #define __ASM_ARCH_REGS_AC97_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <mach/hardware.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * AC97 Controller registers 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define POCR __REG(0x40500000) /* PCM Out Control Register */ 12*4882a593Smuzhiyun #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 13*4882a593Smuzhiyun #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define PICR __REG(0x40500004) /* PCM In Control Register */ 16*4882a593Smuzhiyun #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 17*4882a593Smuzhiyun #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MCCR __REG(0x40500008) /* Mic In Control Register */ 20*4882a593Smuzhiyun #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 21*4882a593Smuzhiyun #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define GCR __REG(0x4050000C) /* Global Control Register */ 24*4882a593Smuzhiyun #ifdef CONFIG_PXA3xx 25*4882a593Smuzhiyun #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ 28*4882a593Smuzhiyun #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ 29*4882a593Smuzhiyun #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ 30*4882a593Smuzhiyun #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ 31*4882a593Smuzhiyun #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ 32*4882a593Smuzhiyun #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ 33*4882a593Smuzhiyun #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ 34*4882a593Smuzhiyun #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ 35*4882a593Smuzhiyun #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ 36*4882a593Smuzhiyun #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ 37*4882a593Smuzhiyun #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define POSR __REG(0x40500010) /* PCM Out Status Register */ 40*4882a593Smuzhiyun #define POSR_FIFOE (1 << 4) /* FIFO error */ 41*4882a593Smuzhiyun #define POSR_FSR (1 << 2) /* FIFO Service Request */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define PISR __REG(0x40500014) /* PCM In Status Register */ 44*4882a593Smuzhiyun #define PISR_FIFOE (1 << 4) /* FIFO error */ 45*4882a593Smuzhiyun #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 46*4882a593Smuzhiyun #define PISR_FSR (1 << 2) /* FIFO Service Request */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define MCSR __REG(0x40500018) /* Mic In Status Register */ 49*4882a593Smuzhiyun #define MCSR_FIFOE (1 << 4) /* FIFO error */ 50*4882a593Smuzhiyun #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 51*4882a593Smuzhiyun #define MCSR_FSR (1 << 2) /* FIFO Service Request */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define GSR __REG(0x4050001C) /* Global Status Register */ 54*4882a593Smuzhiyun #define GSR_CDONE (1 << 19) /* Command Done */ 55*4882a593Smuzhiyun #define GSR_SDONE (1 << 18) /* Status Done */ 56*4882a593Smuzhiyun #define GSR_RDCS (1 << 15) /* Read Completion Status */ 57*4882a593Smuzhiyun #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ 58*4882a593Smuzhiyun #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ 59*4882a593Smuzhiyun #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ 60*4882a593Smuzhiyun #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ 61*4882a593Smuzhiyun #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ 62*4882a593Smuzhiyun #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ 63*4882a593Smuzhiyun #define GSR_PCR (1 << 8) /* Primary Codec Ready */ 64*4882a593Smuzhiyun #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ 65*4882a593Smuzhiyun #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ 66*4882a593Smuzhiyun #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ 67*4882a593Smuzhiyun #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ 68*4882a593Smuzhiyun #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ 69*4882a593Smuzhiyun #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ 70*4882a593Smuzhiyun #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define CAR __REG(0x40500020) /* CODEC Access Register */ 73*4882a593Smuzhiyun #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ 76*4882a593Smuzhiyun #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define MOCR __REG(0x40500100) /* Modem Out Control Register */ 79*4882a593Smuzhiyun #define MOCR_FEIE (1 << 3) /* FIFO Error */ 80*4882a593Smuzhiyun #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define MICR __REG(0x40500108) /* Modem In Control Register */ 83*4882a593Smuzhiyun #define MICR_FEIE (1 << 3) /* FIFO Error */ 84*4882a593Smuzhiyun #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define MOSR __REG(0x40500110) /* Modem Out Status Register */ 87*4882a593Smuzhiyun #define MOSR_FIFOE (1 << 4) /* FIFO error */ 88*4882a593Smuzhiyun #define MOSR_FSR (1 << 2) /* FIFO Service Request */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define MISR __REG(0x40500118) /* Modem In Status Register */ 91*4882a593Smuzhiyun #define MISR_FIFOE (1 << 4) /* FIFO error */ 92*4882a593Smuzhiyun #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 93*4882a593Smuzhiyun #define MISR_FSR (1 << 2) /* FIFO Service Request */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ 98*4882a593Smuzhiyun #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ 99*4882a593Smuzhiyun #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ 100*4882a593Smuzhiyun #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* __ASM_ARCH_REGS_AC97_H */ 103