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/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) argument
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) argument
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) argument
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) argument
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) argument
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) argument
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) argument
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) argument
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) argument
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) argument
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H A Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) argument
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) argument
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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H A Drv515d.h210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) argument
211 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) argument
213 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) argument
214 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) argument
216 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) argument
217 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) argument
219 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) argument
220 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) argument
222 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) argument
223 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) argument
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H A Drs690d.h34 #define G_00005F_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) argument
36 #define S_000078_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) argument
37 #define G_000078_MC_IND_ADDR(x) (((x) >> 0) & 0x1FF) argument
39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9) argument
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1) argument
43 #define S_00007C_MC_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
44 #define G_00007C_MC_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
47 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
48 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
51 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
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H A Dr300d.h70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
71 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
73 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
74 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
77 #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) argument
78 #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) argument
80 #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) argument
81 #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) argument
84 #define S_00015C_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) argument
85 #define G_00015C_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) argument
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H A Dr420d.h32 #define S_0001F8_MC_IND_ADDR(x) (((x) & 0x7F) << 0) argument
33 #define G_0001F8_MC_IND_ADDR(x) (((x) >> 0) & 0x7F) argument
35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) argument
36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) argument
39 #define S_0001FC_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) argument
40 #define G_0001FC_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) argument
43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
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H A Dr600d.h60 #define BACKEND_DISABLE(x) ((x) << 16) argument
63 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) argument
64 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) argument
83 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) argument
84 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) argument
86 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) argument
87 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) argument
97 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) argument
98 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) argument
100 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) argument
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H A Dr520d.h33 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) argument
34 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) argument
37 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) argument
38 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) argument
41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) argument
45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) argument
47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) argument
48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) argument
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H A Devergreend.h53 #define HOST_SMC_MSG(x) ((x) << 0) argument
56 #define HOST_SMC_RESP(x) ((x) << 8) argument
59 #define SMC_HOST_MSG(x) ((x) << 16) argument
62 #define SMC_HOST_RESP(x) ((x) << 24) argument
67 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) argument
70 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) argument
78 #define SPLL_REF_DIV(x) ((x) << 4) argument
80 #define SPLL_PDIV_A(x) ((x) << 20) argument
83 #define SCLK_MUX_SEL(x) ((x) << 0) argument
87 #define SPLL_FB_DIV(x) ((x) << 0) argument
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H A Drs400d.h33 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
34 #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
36 #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
37 #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
40 #define S_00015C_MC_FB_START(x) (((x) & 0xFFFF) << 0) argument
41 #define G_00015C_MC_FB_START(x) (((x) >> 0) & 0xFFFF) argument
43 #define S_00015C_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) argument
44 #define G_00015C_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) argument
47 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) argument
48 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) argument
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/OK3568_Linux_fs/u-boot/include/andestech/
H A Dandes_pcu.h80 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) argument
81 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) argument
86 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) argument
87 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) argument
92 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) argument
93 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) argument
94 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) argument
99 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) argument
100 #define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) argument
101 #define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) argument
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/OK3568_Linux_fs/u-boot/include/synopsys/
H A Ddwcddr21mctl.h48 #define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) argument
49 #define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) argument
50 #define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) argument
51 #define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) argument
52 #define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) argument
53 #define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) argument
54 #define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) argument
55 #define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) argument
56 #define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) argument
57 #define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) argument
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/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu2_reg_tbl.h26 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
27 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
29 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
30 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
32 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
33 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
35 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
36 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
37 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
39 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument
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/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/preprocessor/seq/detail/
H A Dsplit.hpp27 # define BOOST_PP_SEQ_SPLIT_1(x) (x), argument
28 # define BOOST_PP_SEQ_SPLIT_2(x) (x) BOOST_PP_SEQ_SPLIT_1 argument
29 # define BOOST_PP_SEQ_SPLIT_3(x) (x) BOOST_PP_SEQ_SPLIT_2 argument
30 # define BOOST_PP_SEQ_SPLIT_4(x) (x) BOOST_PP_SEQ_SPLIT_3 argument
31 # define BOOST_PP_SEQ_SPLIT_5(x) (x) BOOST_PP_SEQ_SPLIT_4 argument
32 # define BOOST_PP_SEQ_SPLIT_6(x) (x) BOOST_PP_SEQ_SPLIT_5 argument
33 # define BOOST_PP_SEQ_SPLIT_7(x) (x) BOOST_PP_SEQ_SPLIT_6 argument
34 # define BOOST_PP_SEQ_SPLIT_8(x) (x) BOOST_PP_SEQ_SPLIT_7 argument
35 # define BOOST_PP_SEQ_SPLIT_9(x) (x) BOOST_PP_SEQ_SPLIT_8 argument
36 # define BOOST_PP_SEQ_SPLIT_10(x) (x) BOOST_PP_SEQ_SPLIT_9 argument
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/OK3568_Linux_fs/kernel/drivers/staging/media/hantro/
H A Drk3399_vpu_regs.h14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16) argument
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0) argument
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16) argument
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0) argument
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16) argument
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0) argument
23 #define VEPU_REG_VP8_QUT_ZB_DC_CHR(x) (((x) & 0x1ff) << 18) argument
24 #define VEPU_REG_VP8_QUT_ZB_DC_Y2(x) (((x) & 0x1ff) << 9) argument
25 #define VEPU_REG_VP8_QUT_ZB_DC_Y1(x) (((x) & 0x1ff) << 0) argument
27 #define VEPU_REG_VP8_QUT_ZB_AC_CHR(x) (((x) & 0x1ff) << 18) argument
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/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/preprocessor/seq/
H A Denum.hpp31 # define BOOST_PP_SEQ_ENUM_1(x) x argument
32 # define BOOST_PP_SEQ_ENUM_2(x) x, BOOST_PP_SEQ_ENUM_1 argument
33 # define BOOST_PP_SEQ_ENUM_3(x) x, BOOST_PP_SEQ_ENUM_2 argument
34 # define BOOST_PP_SEQ_ENUM_4(x) x, BOOST_PP_SEQ_ENUM_3 argument
35 # define BOOST_PP_SEQ_ENUM_5(x) x, BOOST_PP_SEQ_ENUM_4 argument
36 # define BOOST_PP_SEQ_ENUM_6(x) x, BOOST_PP_SEQ_ENUM_5 argument
37 # define BOOST_PP_SEQ_ENUM_7(x) x, BOOST_PP_SEQ_ENUM_6 argument
38 # define BOOST_PP_SEQ_ENUM_8(x) x, BOOST_PP_SEQ_ENUM_7 argument
39 # define BOOST_PP_SEQ_ENUM_9(x) x, BOOST_PP_SEQ_ENUM_8 argument
40 # define BOOST_PP_SEQ_ENUM_10(x) x, BOOST_PP_SEQ_ENUM_9 argument
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/OK3568_Linux_fs/kernel/lib/crypto/
H A Dchacha.c16 static void chacha_permute(u32 *x, int nrounds) in chacha_permute() argument
24 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 16); in chacha_permute()
25 x[1] += x[5]; x[13] = rol32(x[13] ^ x[1], 16); in chacha_permute()
26 x[2] += x[6]; x[14] = rol32(x[14] ^ x[2], 16); in chacha_permute()
27 x[3] += x[7]; x[15] = rol32(x[15] ^ x[3], 16); in chacha_permute()
29 x[8] += x[12]; x[4] = rol32(x[4] ^ x[8], 12); in chacha_permute()
30 x[9] += x[13]; x[5] = rol32(x[5] ^ x[9], 12); in chacha_permute()
31 x[10] += x[14]; x[6] = rol32(x[6] ^ x[10], 12); in chacha_permute()
32 x[11] += x[15]; x[7] = rol32(x[7] ^ x[11], 12); in chacha_permute()
34 x[0] += x[4]; x[12] = rol32(x[12] ^ x[0], 8); in chacha_permute()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb/
H A Dregs.h45 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) argument
49 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) argument
53 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) argument
57 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) argument
61 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) argument
65 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) argument
70 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) argument
71 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) argument
74 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) argument
78 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) argument
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/OK3568_Linux_fs/u-boot/board/samsung/odroid/
H A Dsetup.h12 #define SDIV(x) ((x) & 0x7) argument
13 #define PDIV(x) (((x) & 0x3f) << 8) argument
14 #define MDIV(x) (((x) & 0x3ff) << 16) argument
15 #define FSEL(x) (((x) & 0x1) << 27) argument
17 #define PLL_ENABLE(x) (((x) & 0x1) << 31) argument
20 #define MUX_APLL_SEL(x) ((x) & 0x1) argument
21 #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) argument
22 #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) argument
23 #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) argument
28 #define APLL_SEL(x) ((x) & 0x7) argument
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/hal/halmac/
H A Dhalmac_bit_8814b.h114 #define BIT_VPDIDX_8814B(x) \ argument
115 (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B)
117 #define BIT_CLEAR_VPDIDX_8814B(x) ((x) & (~BITS_VPDIDX_8814B)) argument
118 #define BIT_GET_VPDIDX_8814B(x) \ argument
119 (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B)
120 #define BIT_SET_VPDIDX_8814B(x, v) \ argument
121 (BIT_CLEAR_VPDIDX_8814B(x) | BIT_VPDIDX_8814B(v))
125 #define BIT_EEM1_0_8814B(x) \ argument
126 (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B)
128 #define BIT_CLEAR_EEM1_0_8814B(x) ((x) & (~BITS_EEM1_0_8814B)) argument
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H A Dhalmac_bit_8822b.h110 #define BIT_VPDIDX_8822B(x) \ argument
111 (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B)
113 #define BIT_CLEAR_VPDIDX_8822B(x) ((x) & (~BITS_VPDIDX_8822B)) argument
114 #define BIT_GET_VPDIDX_8822B(x) \ argument
115 (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B)
116 #define BIT_SET_VPDIDX_8822B(x, v) \ argument
117 (BIT_CLEAR_VPDIDX_8822B(x) | BIT_VPDIDX_8822B(v))
121 #define BIT_EEM1_0_8822B(x) \ argument
122 (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B)
124 #define BIT_CLEAR_EEM1_0_8822B(x) ((x) & (~BITS_EEM1_0_8822B)) argument
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/halmac/
H A Dhalmac_bit_8814b.h113 #define BIT_VPDIDX_8814B(x) \ argument
114 (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B)
116 #define BIT_CLEAR_VPDIDX_8814B(x) ((x) & (~BITS_VPDIDX_8814B)) argument
117 #define BIT_GET_VPDIDX_8814B(x) \ argument
118 (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B)
119 #define BIT_SET_VPDIDX_8814B(x, v) \ argument
120 (BIT_CLEAR_VPDIDX_8814B(x) | BIT_VPDIDX_8814B(v))
124 #define BIT_EEM1_0_8814B(x) \ argument
125 (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B)
127 #define BIT_CLEAR_EEM1_0_8814B(x) ((x) & (~BITS_EEM1_0_8814B)) argument
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H A Dhalmac_bit_8822b.h109 #define BIT_VPDIDX_8822B(x) \ argument
110 (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B)
112 #define BIT_CLEAR_VPDIDX_8822B(x) ((x) & (~BITS_VPDIDX_8822B)) argument
113 #define BIT_GET_VPDIDX_8822B(x) \ argument
114 (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B)
115 #define BIT_SET_VPDIDX_8822B(x, v) \ argument
116 (BIT_CLEAR_VPDIDX_8822B(x) | BIT_VPDIDX_8822B(v))
120 #define BIT_EEM1_0_8822B(x) \ argument
121 (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B)
123 #define BIT_CLEAR_EEM1_0_8822B(x) ((x) & (~BITS_EEM1_0_8822B)) argument
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/hal/halmac/
H A Dhalmac_bit_8814b.h113 #define BIT_VPDIDX_8814B(x) \ argument
114 (((x) & BIT_MASK_VPDIDX_8814B) << BIT_SHIFT_VPDIDX_8814B)
116 #define BIT_CLEAR_VPDIDX_8814B(x) ((x) & (~BITS_VPDIDX_8814B)) argument
117 #define BIT_GET_VPDIDX_8814B(x) \ argument
118 (((x) >> BIT_SHIFT_VPDIDX_8814B) & BIT_MASK_VPDIDX_8814B)
119 #define BIT_SET_VPDIDX_8814B(x, v) \ argument
120 (BIT_CLEAR_VPDIDX_8814B(x) | BIT_VPDIDX_8814B(v))
124 #define BIT_EEM1_0_8814B(x) \ argument
125 (((x) & BIT_MASK_EEM1_0_8814B) << BIT_SHIFT_EEM1_0_8814B)
127 #define BIT_CLEAR_EEM1_0_8814B(x) ((x) & (~BITS_EEM1_0_8814B)) argument
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H A Dhalmac_bit_8822b.h109 #define BIT_VPDIDX_8822B(x) \ argument
110 (((x) & BIT_MASK_VPDIDX_8822B) << BIT_SHIFT_VPDIDX_8822B)
112 #define BIT_CLEAR_VPDIDX_8822B(x) ((x) & (~BITS_VPDIDX_8822B)) argument
113 #define BIT_GET_VPDIDX_8822B(x) \ argument
114 (((x) >> BIT_SHIFT_VPDIDX_8822B) & BIT_MASK_VPDIDX_8822B)
115 #define BIT_SET_VPDIDX_8822B(x, v) \ argument
116 (BIT_CLEAR_VPDIDX_8822B(x) | BIT_VPDIDX_8822B(v))
120 #define BIT_EEM1_0_8822B(x) \ argument
121 (((x) & BIT_MASK_EEM1_0_8822B) << BIT_SHIFT_EEM1_0_8822B)
123 #define BIT_CLEAR_EEM1_0_8822B(x) ((x) & (~BITS_EEM1_0_8822B)) argument
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