1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * Copyright 2008 Red Hat Inc. 4*4882a593Smuzhiyun * Copyright 2009 Jerome Glisse. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 7*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 8*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 9*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 11*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 14*4882a593Smuzhiyun * all copies or substantial portions of the Software. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Authors: Dave Airlie 25*4882a593Smuzhiyun * Alex Deucher 26*4882a593Smuzhiyun * Jerome Glisse 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #ifndef __RV515D_H__ 29*4882a593Smuzhiyun #define __RV515D_H__ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * RV515 registers 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define PCIE_INDEX 0x0030 35*4882a593Smuzhiyun #define PCIE_DATA 0x0034 36*4882a593Smuzhiyun #define MC_IND_INDEX 0x0070 37*4882a593Smuzhiyun #define MC_IND_WR_EN (1 << 24) 38*4882a593Smuzhiyun #define MC_IND_DATA 0x0074 39*4882a593Smuzhiyun #define RBBM_SOFT_RESET 0x00F0 40*4882a593Smuzhiyun #define CONFIG_MEMSIZE 0x00F8 41*4882a593Smuzhiyun #define HDP_FB_LOCATION 0x0134 42*4882a593Smuzhiyun #define CP_CSQ_CNTL 0x0740 43*4882a593Smuzhiyun #define CP_CSQ_MODE 0x0744 44*4882a593Smuzhiyun #define CP_CSQ_ADDR 0x07F0 45*4882a593Smuzhiyun #define CP_CSQ_DATA 0x07F4 46*4882a593Smuzhiyun #define CP_CSQ_STAT 0x07F8 47*4882a593Smuzhiyun #define CP_CSQ2_STAT 0x07FC 48*4882a593Smuzhiyun #define RBBM_STATUS 0x0E40 49*4882a593Smuzhiyun #define DST_PIPE_CONFIG 0x170C 50*4882a593Smuzhiyun #define WAIT_UNTIL 0x1720 51*4882a593Smuzhiyun #define WAIT_2D_IDLE (1 << 14) 52*4882a593Smuzhiyun #define WAIT_3D_IDLE (1 << 15) 53*4882a593Smuzhiyun #define WAIT_2D_IDLECLEAN (1 << 16) 54*4882a593Smuzhiyun #define WAIT_3D_IDLECLEAN (1 << 17) 55*4882a593Smuzhiyun #define ISYNC_CNTL 0x1724 56*4882a593Smuzhiyun #define ISYNC_ANY2D_IDLE3D (1 << 0) 57*4882a593Smuzhiyun #define ISYNC_ANY3D_IDLE2D (1 << 1) 58*4882a593Smuzhiyun #define ISYNC_TRIG2D_IDLE3D (1 << 2) 59*4882a593Smuzhiyun #define ISYNC_TRIG3D_IDLE2D (1 << 3) 60*4882a593Smuzhiyun #define ISYNC_WAIT_IDLEGUI (1 << 4) 61*4882a593Smuzhiyun #define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 62*4882a593Smuzhiyun #define VAP_INDEX_OFFSET 0x208C 63*4882a593Smuzhiyun #define VAP_PVS_STATE_FLUSH_REG 0x2284 64*4882a593Smuzhiyun #define GB_ENABLE 0x4008 65*4882a593Smuzhiyun #define GB_MSPOS0 0x4010 66*4882a593Smuzhiyun #define MS_X0_SHIFT 0 67*4882a593Smuzhiyun #define MS_Y0_SHIFT 4 68*4882a593Smuzhiyun #define MS_X1_SHIFT 8 69*4882a593Smuzhiyun #define MS_Y1_SHIFT 12 70*4882a593Smuzhiyun #define MS_X2_SHIFT 16 71*4882a593Smuzhiyun #define MS_Y2_SHIFT 20 72*4882a593Smuzhiyun #define MSBD0_Y_SHIFT 24 73*4882a593Smuzhiyun #define MSBD0_X_SHIFT 28 74*4882a593Smuzhiyun #define GB_MSPOS1 0x4014 75*4882a593Smuzhiyun #define MS_X3_SHIFT 0 76*4882a593Smuzhiyun #define MS_Y3_SHIFT 4 77*4882a593Smuzhiyun #define MS_X4_SHIFT 8 78*4882a593Smuzhiyun #define MS_Y4_SHIFT 12 79*4882a593Smuzhiyun #define MS_X5_SHIFT 16 80*4882a593Smuzhiyun #define MS_Y5_SHIFT 20 81*4882a593Smuzhiyun #define MSBD1_SHIFT 24 82*4882a593Smuzhiyun #define GB_TILE_CONFIG 0x4018 83*4882a593Smuzhiyun #define ENABLE_TILING (1 << 0) 84*4882a593Smuzhiyun #define PIPE_COUNT_MASK 0x0000000E 85*4882a593Smuzhiyun #define PIPE_COUNT_SHIFT 1 86*4882a593Smuzhiyun #define TILE_SIZE_8 (0 << 4) 87*4882a593Smuzhiyun #define TILE_SIZE_16 (1 << 4) 88*4882a593Smuzhiyun #define TILE_SIZE_32 (2 << 4) 89*4882a593Smuzhiyun #define SUBPIXEL_1_12 (0 << 16) 90*4882a593Smuzhiyun #define SUBPIXEL_1_16 (1 << 16) 91*4882a593Smuzhiyun #define GB_SELECT 0x401C 92*4882a593Smuzhiyun #define GB_AA_CONFIG 0x4020 93*4882a593Smuzhiyun #define GB_PIPE_SELECT 0x402C 94*4882a593Smuzhiyun #define GA_ENHANCE 0x4274 95*4882a593Smuzhiyun #define GA_DEADLOCK_CNTL (1 << 0) 96*4882a593Smuzhiyun #define GA_FASTSYNC_CNTL (1 << 1) 97*4882a593Smuzhiyun #define GA_POLY_MODE 0x4288 98*4882a593Smuzhiyun #define FRONT_PTYPE_POINT (0 << 4) 99*4882a593Smuzhiyun #define FRONT_PTYPE_LINE (1 << 4) 100*4882a593Smuzhiyun #define FRONT_PTYPE_TRIANGE (2 << 4) 101*4882a593Smuzhiyun #define BACK_PTYPE_POINT (0 << 7) 102*4882a593Smuzhiyun #define BACK_PTYPE_LINE (1 << 7) 103*4882a593Smuzhiyun #define BACK_PTYPE_TRIANGE (2 << 7) 104*4882a593Smuzhiyun #define GA_ROUND_MODE 0x428C 105*4882a593Smuzhiyun #define GEOMETRY_ROUND_TRUNC (0 << 0) 106*4882a593Smuzhiyun #define GEOMETRY_ROUND_NEAREST (1 << 0) 107*4882a593Smuzhiyun #define COLOR_ROUND_TRUNC (0 << 2) 108*4882a593Smuzhiyun #define COLOR_ROUND_NEAREST (1 << 2) 109*4882a593Smuzhiyun #define SU_REG_DEST 0x42C8 110*4882a593Smuzhiyun #define RB3D_DSTCACHE_CTLSTAT 0x4E4C 111*4882a593Smuzhiyun #define RB3D_DC_FLUSH (2 << 0) 112*4882a593Smuzhiyun #define RB3D_DC_FREE (2 << 2) 113*4882a593Smuzhiyun #define RB3D_DC_FINISH (1 << 4) 114*4882a593Smuzhiyun #define ZB_ZCACHE_CTLSTAT 0x4F18 115*4882a593Smuzhiyun #define ZC_FLUSH (1 << 0) 116*4882a593Smuzhiyun #define ZC_FREE (1 << 1) 117*4882a593Smuzhiyun #define DC_LB_MEMORY_SPLIT 0x6520 118*4882a593Smuzhiyun #define DC_LB_MEMORY_SPLIT_MASK 0x00000003 119*4882a593Smuzhiyun #define DC_LB_MEMORY_SPLIT_SHIFT 0 120*4882a593Smuzhiyun #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 121*4882a593Smuzhiyun #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 122*4882a593Smuzhiyun #define DC_LB_MEMORY_SPLIT_D1_ONLY 2 123*4882a593Smuzhiyun #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 124*4882a593Smuzhiyun #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) 125*4882a593Smuzhiyun #define DC_LB_DISP1_END_ADR_SHIFT 4 126*4882a593Smuzhiyun #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 127*4882a593Smuzhiyun #define D1MODE_PRIORITY_A_CNT 0x6548 128*4882a593Smuzhiyun #define MODE_PRIORITY_MARK_MASK 0x00007FFF 129*4882a593Smuzhiyun #define MODE_PRIORITY_OFF (1 << 16) 130*4882a593Smuzhiyun #define MODE_PRIORITY_ALWAYS_ON (1 << 20) 131*4882a593Smuzhiyun #define MODE_PRIORITY_FORCE_MASK (1 << 24) 132*4882a593Smuzhiyun #define D1MODE_PRIORITY_B_CNT 0x654C 133*4882a593Smuzhiyun #define LB_MAX_REQ_OUTSTANDING 0x6D58 134*4882a593Smuzhiyun #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F 135*4882a593Smuzhiyun #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 136*4882a593Smuzhiyun #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 137*4882a593Smuzhiyun #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 138*4882a593Smuzhiyun #define D2MODE_PRIORITY_A_CNT 0x6D48 139*4882a593Smuzhiyun #define D2MODE_PRIORITY_B_CNT 0x6D4C 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* ix[MC] registers */ 142*4882a593Smuzhiyun #define MC_FB_LOCATION 0x01 143*4882a593Smuzhiyun #define MC_FB_START_MASK 0x0000FFFF 144*4882a593Smuzhiyun #define MC_FB_START_SHIFT 0 145*4882a593Smuzhiyun #define MC_FB_TOP_MASK 0xFFFF0000 146*4882a593Smuzhiyun #define MC_FB_TOP_SHIFT 16 147*4882a593Smuzhiyun #define MC_AGP_LOCATION 0x02 148*4882a593Smuzhiyun #define MC_AGP_START_MASK 0x0000FFFF 149*4882a593Smuzhiyun #define MC_AGP_START_SHIFT 0 150*4882a593Smuzhiyun #define MC_AGP_TOP_MASK 0xFFFF0000 151*4882a593Smuzhiyun #define MC_AGP_TOP_SHIFT 16 152*4882a593Smuzhiyun #define MC_AGP_BASE 0x03 153*4882a593Smuzhiyun #define MC_AGP_BASE_2 0x04 154*4882a593Smuzhiyun #define MC_CNTL 0x5 155*4882a593Smuzhiyun #define MEM_NUM_CHANNELS_MASK 0x00000003 156*4882a593Smuzhiyun #define MC_STATUS 0x08 157*4882a593Smuzhiyun #define MC_STATUS_IDLE (1 << 4) 158*4882a593Smuzhiyun #define MC_MISC_LAT_TIMER 0x09 159*4882a593Smuzhiyun #define MC_CPR_INIT_LAT_MASK 0x0000000F 160*4882a593Smuzhiyun #define MC_VF_INIT_LAT_MASK 0x000000F0 161*4882a593Smuzhiyun #define MC_DISP0R_INIT_LAT_MASK 0x00000F00 162*4882a593Smuzhiyun #define MC_DISP0R_INIT_LAT_SHIFT 8 163*4882a593Smuzhiyun #define MC_DISP1R_INIT_LAT_MASK 0x0000F000 164*4882a593Smuzhiyun #define MC_DISP1R_INIT_LAT_SHIFT 12 165*4882a593Smuzhiyun #define MC_FIXED_INIT_LAT_MASK 0x000F0000 166*4882a593Smuzhiyun #define MC_E2R_INIT_LAT_MASK 0x00F00000 167*4882a593Smuzhiyun #define SAME_PAGE_PRIO_MASK 0x0F000000 168*4882a593Smuzhiyun #define MC_GLOBW_INIT_LAT_MASK 0xF0000000 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 172*4882a593Smuzhiyun * PM4 packet 173*4882a593Smuzhiyun */ 174*4882a593Smuzhiyun #define CP_PACKET0 0x00000000 175*4882a593Smuzhiyun #define PACKET0_BASE_INDEX_SHIFT 0 176*4882a593Smuzhiyun #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 177*4882a593Smuzhiyun #define PACKET0_COUNT_SHIFT 16 178*4882a593Smuzhiyun #define PACKET0_COUNT_MASK (0x3fff << 16) 179*4882a593Smuzhiyun #define CP_PACKET1 0x40000000 180*4882a593Smuzhiyun #define CP_PACKET2 0x80000000 181*4882a593Smuzhiyun #define PACKET2_PAD_SHIFT 0 182*4882a593Smuzhiyun #define PACKET2_PAD_MASK (0x3fffffff << 0) 183*4882a593Smuzhiyun #define CP_PACKET3 0xC0000000 184*4882a593Smuzhiyun #define PACKET3_IT_OPCODE_SHIFT 8 185*4882a593Smuzhiyun #define PACKET3_IT_OPCODE_MASK (0xff << 8) 186*4882a593Smuzhiyun #define PACKET3_COUNT_SHIFT 16 187*4882a593Smuzhiyun #define PACKET3_COUNT_MASK (0x3fff << 16) 188*4882a593Smuzhiyun /* PACKET3 op code */ 189*4882a593Smuzhiyun #define PACKET3_NOP 0x10 190*4882a593Smuzhiyun #define PACKET3_3D_DRAW_VBUF 0x28 191*4882a593Smuzhiyun #define PACKET3_3D_DRAW_IMMD 0x29 192*4882a593Smuzhiyun #define PACKET3_3D_DRAW_INDX 0x2A 193*4882a593Smuzhiyun #define PACKET3_3D_LOAD_VBPNTR 0x2F 194*4882a593Smuzhiyun #define PACKET3_INDX_BUFFER 0x33 195*4882a593Smuzhiyun #define PACKET3_3D_DRAW_VBUF_2 0x34 196*4882a593Smuzhiyun #define PACKET3_3D_DRAW_IMMD_2 0x35 197*4882a593Smuzhiyun #define PACKET3_3D_DRAW_INDX_2 0x36 198*4882a593Smuzhiyun #define PACKET3_BITBLT_MULTI 0x9B 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define PACKET0(reg, n) (CP_PACKET0 | \ 201*4882a593Smuzhiyun REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 202*4882a593Smuzhiyun REG_SET(PACKET0_COUNT, (n))) 203*4882a593Smuzhiyun #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 204*4882a593Smuzhiyun #define PACKET3(op, n) (CP_PACKET3 | \ 205*4882a593Smuzhiyun REG_SET(PACKET3_IT_OPCODE, (op)) | \ 206*4882a593Smuzhiyun REG_SET(PACKET3_COUNT, (n))) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* Registers */ 209*4882a593Smuzhiyun #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 210*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 211*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 212*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 213*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 214*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 215*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 216*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) 217*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) 218*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB 219*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 220*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 221*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 222*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 223*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 224*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 225*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 226*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 227*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 228*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 229*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 230*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 231*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 232*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 233*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 234*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 235*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 236*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 237*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 238*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 239*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 240*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 241*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 242*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 243*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 244*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 245*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 246*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 247*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 248*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 249*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) 250*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) 251*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF 252*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) 253*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) 254*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF 255*4882a593Smuzhiyun #define R_0000F8_CONFIG_MEMSIZE 0x0000F8 256*4882a593Smuzhiyun #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) 257*4882a593Smuzhiyun #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) 258*4882a593Smuzhiyun #define C_0000F8_CONFIG_MEMSIZE 0x00000000 259*4882a593Smuzhiyun #define R_000134_HDP_FB_LOCATION 0x000134 260*4882a593Smuzhiyun #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) 261*4882a593Smuzhiyun #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) 262*4882a593Smuzhiyun #define C_000134_HDP_FB_START 0xFFFF0000 263*4882a593Smuzhiyun #define R_000300_VGA_RENDER_CONTROL 0x000300 264*4882a593Smuzhiyun #define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0) 265*4882a593Smuzhiyun #define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F) 266*4882a593Smuzhiyun #define C_000300_VGA_BLINK_RATE 0xFFFFFFE0 267*4882a593Smuzhiyun #define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5) 268*4882a593Smuzhiyun #define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3) 269*4882a593Smuzhiyun #define C_000300_VGA_BLINK_MODE 0xFFFFFF9F 270*4882a593Smuzhiyun #define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7) 271*4882a593Smuzhiyun #define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1) 272*4882a593Smuzhiyun #define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F 273*4882a593Smuzhiyun #define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8) 274*4882a593Smuzhiyun #define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1) 275*4882a593Smuzhiyun #define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF 276*4882a593Smuzhiyun #define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16) 277*4882a593Smuzhiyun #define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3) 278*4882a593Smuzhiyun #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 279*4882a593Smuzhiyun #define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24) 280*4882a593Smuzhiyun #define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1) 281*4882a593Smuzhiyun #define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF 282*4882a593Smuzhiyun #define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25) 283*4882a593Smuzhiyun #define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1) 284*4882a593Smuzhiyun #define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF 285*4882a593Smuzhiyun #define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310 286*4882a593Smuzhiyun #define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 287*4882a593Smuzhiyun #define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 288*4882a593Smuzhiyun #define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000 289*4882a593Smuzhiyun #define R_000328_VGA_HDP_CONTROL 0x000328 290*4882a593Smuzhiyun #define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0) 291*4882a593Smuzhiyun #define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1) 292*4882a593Smuzhiyun #define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE 293*4882a593Smuzhiyun #define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8) 294*4882a593Smuzhiyun #define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1) 295*4882a593Smuzhiyun #define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF 296*4882a593Smuzhiyun #define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16) 297*4882a593Smuzhiyun #define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1) 298*4882a593Smuzhiyun #define C_000328_VGA_SOFT_RESET 0xFFFEFFFF 299*4882a593Smuzhiyun #define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24) 300*4882a593Smuzhiyun #define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1) 301*4882a593Smuzhiyun #define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF 302*4882a593Smuzhiyun #define R_000330_D1VGA_CONTROL 0x000330 303*4882a593Smuzhiyun #define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) 304*4882a593Smuzhiyun #define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) 305*4882a593Smuzhiyun #define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE 306*4882a593Smuzhiyun #define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) 307*4882a593Smuzhiyun #define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) 308*4882a593Smuzhiyun #define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF 309*4882a593Smuzhiyun #define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) 310*4882a593Smuzhiyun #define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) 311*4882a593Smuzhiyun #define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF 312*4882a593Smuzhiyun #define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) 313*4882a593Smuzhiyun #define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) 314*4882a593Smuzhiyun #define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF 315*4882a593Smuzhiyun #define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) 316*4882a593Smuzhiyun #define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) 317*4882a593Smuzhiyun #define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF 318*4882a593Smuzhiyun #define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24) 319*4882a593Smuzhiyun #define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3) 320*4882a593Smuzhiyun #define C_000330_D1VGA_ROTATE 0xFCFFFFFF 321*4882a593Smuzhiyun #define R_000338_D2VGA_CONTROL 0x000338 322*4882a593Smuzhiyun #define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) 323*4882a593Smuzhiyun #define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) 324*4882a593Smuzhiyun #define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE 325*4882a593Smuzhiyun #define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) 326*4882a593Smuzhiyun #define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) 327*4882a593Smuzhiyun #define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF 328*4882a593Smuzhiyun #define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) 329*4882a593Smuzhiyun #define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) 330*4882a593Smuzhiyun #define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF 331*4882a593Smuzhiyun #define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) 332*4882a593Smuzhiyun #define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) 333*4882a593Smuzhiyun #define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF 334*4882a593Smuzhiyun #define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) 335*4882a593Smuzhiyun #define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) 336*4882a593Smuzhiyun #define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF 337*4882a593Smuzhiyun #define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24) 338*4882a593Smuzhiyun #define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3) 339*4882a593Smuzhiyun #define C_000338_D2VGA_ROTATE 0xFCFFFFFF 340*4882a593Smuzhiyun #define R_0007C0_CP_STAT 0x0007C0 341*4882a593Smuzhiyun #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 342*4882a593Smuzhiyun #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 343*4882a593Smuzhiyun #define C_0007C0_MRU_BUSY 0xFFFFFFFE 344*4882a593Smuzhiyun #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 345*4882a593Smuzhiyun #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 346*4882a593Smuzhiyun #define C_0007C0_MWU_BUSY 0xFFFFFFFD 347*4882a593Smuzhiyun #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 348*4882a593Smuzhiyun #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 349*4882a593Smuzhiyun #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 350*4882a593Smuzhiyun #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 351*4882a593Smuzhiyun #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 352*4882a593Smuzhiyun #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 353*4882a593Smuzhiyun #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 354*4882a593Smuzhiyun #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 355*4882a593Smuzhiyun #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 356*4882a593Smuzhiyun #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 357*4882a593Smuzhiyun #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 358*4882a593Smuzhiyun #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 359*4882a593Smuzhiyun #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 360*4882a593Smuzhiyun #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 361*4882a593Smuzhiyun #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 362*4882a593Smuzhiyun #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 363*4882a593Smuzhiyun #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 364*4882a593Smuzhiyun #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 365*4882a593Smuzhiyun #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 366*4882a593Smuzhiyun #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 367*4882a593Smuzhiyun #define C_0007C0_CSI_BUSY 0xFFFFDFFF 368*4882a593Smuzhiyun #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) 369*4882a593Smuzhiyun #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) 370*4882a593Smuzhiyun #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF 371*4882a593Smuzhiyun #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) 372*4882a593Smuzhiyun #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) 373*4882a593Smuzhiyun #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF 374*4882a593Smuzhiyun #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 375*4882a593Smuzhiyun #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 376*4882a593Smuzhiyun #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 377*4882a593Smuzhiyun #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 378*4882a593Smuzhiyun #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 379*4882a593Smuzhiyun #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 380*4882a593Smuzhiyun #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 381*4882a593Smuzhiyun #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 382*4882a593Smuzhiyun #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 383*4882a593Smuzhiyun #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 384*4882a593Smuzhiyun #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 385*4882a593Smuzhiyun #define C_0007C0_CP_BUSY 0x7FFFFFFF 386*4882a593Smuzhiyun #define R_000E40_RBBM_STATUS 0x000E40 387*4882a593Smuzhiyun #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 388*4882a593Smuzhiyun #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 389*4882a593Smuzhiyun #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 390*4882a593Smuzhiyun #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 391*4882a593Smuzhiyun #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 392*4882a593Smuzhiyun #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 393*4882a593Smuzhiyun #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 394*4882a593Smuzhiyun #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 395*4882a593Smuzhiyun #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 396*4882a593Smuzhiyun #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 397*4882a593Smuzhiyun #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 398*4882a593Smuzhiyun #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 399*4882a593Smuzhiyun #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 400*4882a593Smuzhiyun #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 401*4882a593Smuzhiyun #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 402*4882a593Smuzhiyun #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 403*4882a593Smuzhiyun #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 404*4882a593Smuzhiyun #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 405*4882a593Smuzhiyun #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 406*4882a593Smuzhiyun #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 407*4882a593Smuzhiyun #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 408*4882a593Smuzhiyun #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 409*4882a593Smuzhiyun #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 410*4882a593Smuzhiyun #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 411*4882a593Smuzhiyun #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 412*4882a593Smuzhiyun #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 413*4882a593Smuzhiyun #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 414*4882a593Smuzhiyun #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 415*4882a593Smuzhiyun #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 416*4882a593Smuzhiyun #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 417*4882a593Smuzhiyun #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 418*4882a593Smuzhiyun #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 419*4882a593Smuzhiyun #define C_000E40_E2_BUSY 0xFFFDFFFF 420*4882a593Smuzhiyun #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 421*4882a593Smuzhiyun #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 422*4882a593Smuzhiyun #define C_000E40_RB2D_BUSY 0xFFFBFFFF 423*4882a593Smuzhiyun #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 424*4882a593Smuzhiyun #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 425*4882a593Smuzhiyun #define C_000E40_RB3D_BUSY 0xFFF7FFFF 426*4882a593Smuzhiyun #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) 427*4882a593Smuzhiyun #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) 428*4882a593Smuzhiyun #define C_000E40_VAP_BUSY 0xFFEFFFFF 429*4882a593Smuzhiyun #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 430*4882a593Smuzhiyun #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 431*4882a593Smuzhiyun #define C_000E40_RE_BUSY 0xFFDFFFFF 432*4882a593Smuzhiyun #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 433*4882a593Smuzhiyun #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 434*4882a593Smuzhiyun #define C_000E40_TAM_BUSY 0xFFBFFFFF 435*4882a593Smuzhiyun #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 436*4882a593Smuzhiyun #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 437*4882a593Smuzhiyun #define C_000E40_TDM_BUSY 0xFF7FFFFF 438*4882a593Smuzhiyun #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 439*4882a593Smuzhiyun #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 440*4882a593Smuzhiyun #define C_000E40_PB_BUSY 0xFEFFFFFF 441*4882a593Smuzhiyun #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) 442*4882a593Smuzhiyun #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) 443*4882a593Smuzhiyun #define C_000E40_TIM_BUSY 0xFDFFFFFF 444*4882a593Smuzhiyun #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) 445*4882a593Smuzhiyun #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) 446*4882a593Smuzhiyun #define C_000E40_GA_BUSY 0xFBFFFFFF 447*4882a593Smuzhiyun #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) 448*4882a593Smuzhiyun #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) 449*4882a593Smuzhiyun #define C_000E40_CBA2D_BUSY 0xF7FFFFFF 450*4882a593Smuzhiyun #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) 451*4882a593Smuzhiyun #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) 452*4882a593Smuzhiyun #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF 453*4882a593Smuzhiyun #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) 454*4882a593Smuzhiyun #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) 455*4882a593Smuzhiyun #define C_000E40_SKID_CFBUSY 0xDFFFFFFF 456*4882a593Smuzhiyun #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) 457*4882a593Smuzhiyun #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) 458*4882a593Smuzhiyun #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF 459*4882a593Smuzhiyun #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 460*4882a593Smuzhiyun #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 461*4882a593Smuzhiyun #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 462*4882a593Smuzhiyun #define R_006080_D1CRTC_CONTROL 0x006080 463*4882a593Smuzhiyun #define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0) 464*4882a593Smuzhiyun #define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) 465*4882a593Smuzhiyun #define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE 466*4882a593Smuzhiyun #define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) 467*4882a593Smuzhiyun #define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) 468*4882a593Smuzhiyun #define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF 469*4882a593Smuzhiyun #define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) 470*4882a593Smuzhiyun #define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) 471*4882a593Smuzhiyun #define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF 472*4882a593Smuzhiyun #define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) 473*4882a593Smuzhiyun #define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) 474*4882a593Smuzhiyun #define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF 475*4882a593Smuzhiyun #define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) 476*4882a593Smuzhiyun #define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) 477*4882a593Smuzhiyun #define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF 478*4882a593Smuzhiyun #define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8 479*4882a593Smuzhiyun #define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) 480*4882a593Smuzhiyun #define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) 481*4882a593Smuzhiyun #define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE 482*4882a593Smuzhiyun #define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110 483*4882a593Smuzhiyun #define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 484*4882a593Smuzhiyun #define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 485*4882a593Smuzhiyun #define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 486*4882a593Smuzhiyun #define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118 487*4882a593Smuzhiyun #define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 488*4882a593Smuzhiyun #define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 489*4882a593Smuzhiyun #define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 490*4882a593Smuzhiyun #define R_006880_D2CRTC_CONTROL 0x006880 491*4882a593Smuzhiyun #define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0) 492*4882a593Smuzhiyun #define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) 493*4882a593Smuzhiyun #define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE 494*4882a593Smuzhiyun #define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) 495*4882a593Smuzhiyun #define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) 496*4882a593Smuzhiyun #define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF 497*4882a593Smuzhiyun #define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) 498*4882a593Smuzhiyun #define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) 499*4882a593Smuzhiyun #define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF 500*4882a593Smuzhiyun #define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) 501*4882a593Smuzhiyun #define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) 502*4882a593Smuzhiyun #define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF 503*4882a593Smuzhiyun #define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) 504*4882a593Smuzhiyun #define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) 505*4882a593Smuzhiyun #define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF 506*4882a593Smuzhiyun #define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8 507*4882a593Smuzhiyun #define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) 508*4882a593Smuzhiyun #define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) 509*4882a593Smuzhiyun #define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE 510*4882a593Smuzhiyun #define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910 511*4882a593Smuzhiyun #define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 512*4882a593Smuzhiyun #define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 513*4882a593Smuzhiyun #define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 514*4882a593Smuzhiyun #define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918 515*4882a593Smuzhiyun #define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 516*4882a593Smuzhiyun #define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 517*4882a593Smuzhiyun #define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun #define R_000001_MC_FB_LOCATION 0x000001 521*4882a593Smuzhiyun #define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0) 522*4882a593Smuzhiyun #define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 523*4882a593Smuzhiyun #define C_000001_MC_FB_START 0xFFFF0000 524*4882a593Smuzhiyun #define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 525*4882a593Smuzhiyun #define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 526*4882a593Smuzhiyun #define C_000001_MC_FB_TOP 0x0000FFFF 527*4882a593Smuzhiyun #define R_000002_MC_AGP_LOCATION 0x000002 528*4882a593Smuzhiyun #define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 529*4882a593Smuzhiyun #define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 530*4882a593Smuzhiyun #define C_000002_MC_AGP_START 0xFFFF0000 531*4882a593Smuzhiyun #define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 532*4882a593Smuzhiyun #define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 533*4882a593Smuzhiyun #define C_000002_MC_AGP_TOP 0x0000FFFF 534*4882a593Smuzhiyun #define R_000003_MC_AGP_BASE 0x000003 535*4882a593Smuzhiyun #define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 536*4882a593Smuzhiyun #define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 537*4882a593Smuzhiyun #define C_000003_AGP_BASE_ADDR 0x00000000 538*4882a593Smuzhiyun #define R_000004_MC_AGP_BASE_2 0x000004 539*4882a593Smuzhiyun #define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) 540*4882a593Smuzhiyun #define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) 541*4882a593Smuzhiyun #define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun #define R_00000F_CP_DYN_CNTL 0x00000F 545*4882a593Smuzhiyun #define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0) 546*4882a593Smuzhiyun #define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1) 547*4882a593Smuzhiyun #define C_00000F_CP_FORCEON 0xFFFFFFFE 548*4882a593Smuzhiyun #define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 549*4882a593Smuzhiyun #define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 550*4882a593Smuzhiyun #define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD 551*4882a593Smuzhiyun #define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2) 552*4882a593Smuzhiyun #define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 553*4882a593Smuzhiyun #define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB 554*4882a593Smuzhiyun #define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 555*4882a593Smuzhiyun #define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 556*4882a593Smuzhiyun #define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7 557*4882a593Smuzhiyun #define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 558*4882a593Smuzhiyun #define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 559*4882a593Smuzhiyun #define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F 560*4882a593Smuzhiyun #define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 561*4882a593Smuzhiyun #define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 562*4882a593Smuzhiyun #define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF 563*4882a593Smuzhiyun #define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 564*4882a593Smuzhiyun #define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 565*4882a593Smuzhiyun #define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF 566*4882a593Smuzhiyun #define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 567*4882a593Smuzhiyun #define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 568*4882a593Smuzhiyun #define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF 569*4882a593Smuzhiyun #define S_00000F_SPARE(x) (((x) & 0x3) << 22) 570*4882a593Smuzhiyun #define G_00000F_SPARE(x) (((x) >> 22) & 0x3) 571*4882a593Smuzhiyun #define C_00000F_SPARE 0xFF3FFFFF 572*4882a593Smuzhiyun #define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 573*4882a593Smuzhiyun #define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 574*4882a593Smuzhiyun #define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF 575*4882a593Smuzhiyun #define R_000011_E2_DYN_CNTL 0x000011 576*4882a593Smuzhiyun #define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0) 577*4882a593Smuzhiyun #define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1) 578*4882a593Smuzhiyun #define C_000011_E2_FORCEON 0xFFFFFFFE 579*4882a593Smuzhiyun #define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 580*4882a593Smuzhiyun #define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 581*4882a593Smuzhiyun #define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD 582*4882a593Smuzhiyun #define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2) 583*4882a593Smuzhiyun #define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 584*4882a593Smuzhiyun #define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB 585*4882a593Smuzhiyun #define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 586*4882a593Smuzhiyun #define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 587*4882a593Smuzhiyun #define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7 588*4882a593Smuzhiyun #define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 589*4882a593Smuzhiyun #define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 590*4882a593Smuzhiyun #define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F 591*4882a593Smuzhiyun #define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 592*4882a593Smuzhiyun #define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 593*4882a593Smuzhiyun #define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF 594*4882a593Smuzhiyun #define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 595*4882a593Smuzhiyun #define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 596*4882a593Smuzhiyun #define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF 597*4882a593Smuzhiyun #define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 598*4882a593Smuzhiyun #define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 599*4882a593Smuzhiyun #define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF 600*4882a593Smuzhiyun #define S_000011_SPARE(x) (((x) & 0x3) << 22) 601*4882a593Smuzhiyun #define G_000011_SPARE(x) (((x) >> 22) & 0x3) 602*4882a593Smuzhiyun #define C_000011_SPARE 0xFF3FFFFF 603*4882a593Smuzhiyun #define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 604*4882a593Smuzhiyun #define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 605*4882a593Smuzhiyun #define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF 606*4882a593Smuzhiyun #define R_000013_IDCT_DYN_CNTL 0x000013 607*4882a593Smuzhiyun #define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0) 608*4882a593Smuzhiyun #define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1) 609*4882a593Smuzhiyun #define C_000013_IDCT_FORCEON 0xFFFFFFFE 610*4882a593Smuzhiyun #define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 611*4882a593Smuzhiyun #define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 612*4882a593Smuzhiyun #define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD 613*4882a593Smuzhiyun #define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2) 614*4882a593Smuzhiyun #define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 615*4882a593Smuzhiyun #define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB 616*4882a593Smuzhiyun #define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 617*4882a593Smuzhiyun #define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 618*4882a593Smuzhiyun #define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7 619*4882a593Smuzhiyun #define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 620*4882a593Smuzhiyun #define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 621*4882a593Smuzhiyun #define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F 622*4882a593Smuzhiyun #define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 623*4882a593Smuzhiyun #define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 624*4882a593Smuzhiyun #define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF 625*4882a593Smuzhiyun #define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 626*4882a593Smuzhiyun #define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 627*4882a593Smuzhiyun #define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF 628*4882a593Smuzhiyun #define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 629*4882a593Smuzhiyun #define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 630*4882a593Smuzhiyun #define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF 631*4882a593Smuzhiyun #define S_000013_SPARE(x) (((x) & 0x3) << 22) 632*4882a593Smuzhiyun #define G_000013_SPARE(x) (((x) >> 22) & 0x3) 633*4882a593Smuzhiyun #define C_000013_SPARE 0xFF3FFFFF 634*4882a593Smuzhiyun #define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 635*4882a593Smuzhiyun #define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 636*4882a593Smuzhiyun #define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun #endif 639