| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/ |
| H A D | mce.c | 46 int32_t ret = 0; in mce_command_handler() local
50 ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); in mce_command_handler()
51 if (ret < 0) { in mce_command_handler()
52 ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); in mce_command_handler()
58 ret = nvg_is_sc7_allowed(); in mce_command_handler()
59 if (ret < 0) { in mce_command_handler()
60 ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); in mce_command_handler()
66 ret = nvg_online_core((uint32_t)arg0); in mce_command_handler()
67 if (ret < 0) { in mce_command_handler()
68 ERROR("%s: online_core failed(%d)\n", __func__, ret); in mce_command_handler()
[all …]
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| /rk3399_ARM-atf/plat/st/common/ |
| H A D | stm32mp_crypto_lib.c | 50 int ret; in crypto_lib_init() local
54 ret = stm32_hash_register(); in crypto_lib_init()
55 if (ret != 0) { in crypto_lib_init()
56 ERROR("HASH init (%d)\n", ret); in crypto_lib_init()
85 int ret; in get_plain_pk_from_asn1() local
99 ret = mbedtls_asn1_get_tag(&p, end, len, in get_plain_pk_from_asn1()
101 if (ret != 0) { in get_plain_pk_from_asn1()
106 ret = mbedtls_asn1_get_alg(&p, end, &alg_oid, &alg_params); in get_plain_pk_from_asn1()
107 if (ret != 0) { in get_plain_pk_from_asn1()
108 VERBOSE("%s: mbedtls_asn1_get_alg (%d)\n", __func__, ret); in get_plain_pk_from_asn1()
[all …]
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| /rk3399_ARM-atf/plat/xilinx/common/pm_service/ |
| H A D | pm_svc_main.c | 114 int ret; in request_cpu_pwrdwn() local
119 ret = psci_stop_other_cores(plat_my_core_pos(), PWRDWN_WAIT_TIMEOUT, in request_cpu_pwrdwn()
121 if (ret != PSCI_E_SUCCESS) { in request_cpu_pwrdwn()
139 enum pm_ret_status ret; in ipi_fiq_handler() local
166 ret = pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0); in ipi_fiq_handler()
167 if (ret != PM_RET_SUCCESS) { in ipi_fiq_handler()
168 payload[0] = (uint32_t)ret; in ipi_fiq_handler()
231 int32_t ret = 0; in pm_register_sgi() local
236 ret = -EBUSY; in pm_register_sgi()
238 ret = -EINVAL; in pm_register_sgi()
[all …]
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| /rk3399_ARM-atf/plat/ti/k3low/common/ |
| H A D | am62l_bl31_setup.c | 30 int ret; in ti_soc_init() local
34 ret = ti_sci_boot_notification(); in ti_soc_init()
35 if (ret != 0) { in ti_soc_init()
36 ERROR("%s: Failed to receive boot notification (%d)\n", __func__, ret); in ti_soc_init()
37 return ret; in ti_soc_init()
40 ret = ti_sci_get_revision(&version); in ti_soc_init()
41 if (ret != 0) { in ti_soc_init()
42 ERROR("%s: Failed to get revision (%d)\n", __func__, ret); in ti_soc_init()
43 return ret; in ti_soc_init()
51 ret = ti_sci_proc_request(PLAT_PROC_START_ID); in ti_soc_init()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/dcm/ |
| H A D | mtk_dcm_utils.c | 35 bool ret = true; in dcm_mp_cpusys_top_adb_dcm_is_on() local
37 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) & in dcm_mp_cpusys_top_adb_dcm_is_on()
40 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
44 return ret; in dcm_mp_cpusys_top_adb_dcm_is_on()
80 bool ret = true; in dcm_mp_cpusys_top_apb_dcm_is_on() local
82 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
85 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
88 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
92 return ret; in dcm_mp_cpusys_top_apb_dcm_is_on()
134 bool ret = true; in dcm_mp_cpusys_top_bus_pll_div_dcm_is_on() local
[all …]
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| H A D | mtk_dcm.c | 38 bool ret = true; in check_dcm_state() local
40 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); in check_dcm_state()
41 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); in check_dcm_state()
42 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); in check_dcm_state()
44 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); in check_dcm_state()
45 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); in check_dcm_state()
46 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); in check_dcm_state()
47 ret &= dcm_mp_cpusys_top_cpubiu_dbg_cg_is_on(); in check_dcm_state()
48 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); in check_dcm_state()
49 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); in check_dcm_state()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/apusys_rv/2.0/ |
| H A D | apusys_rv.c | 129 int ret; in hw_sema2_release() local
131 ret = apu_hw_sema_ctl(HW_SEMA2, HW_SEMA_USER, 0, timeout, 0); in hw_sema2_release()
132 if (ret) { in hw_sema2_release()
136 return ret; in hw_sema2_release()
145 int ret; in hw_sema2_acquire() local
147 ret = apu_hw_sema_ctl(HW_SEMA2, HW_SEMA_USER, 1, timeout, 0); in hw_sema2_acquire()
148 if (ret) { in hw_sema2_acquire()
152 return ret; in hw_sema2_acquire()
160 int ret; in apusys_kernel_apusys_rv_stop_mp() local
162 ret = hw_sema2_acquire(HW_SEM_TIMEOUT); in apusys_kernel_apusys_rv_stop_mp()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/dcm/ |
| H A D | mtk_dcm_utils.c | 44 bool ret = true; in dcm_mp_cpusys_top_adb_dcm_is_on() local
46 ret &= ((mmio_read_32(MP_ADB_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
49 ret &= ((mmio_read_32(MP_ADB_DCM_CFG4) & in dcm_mp_cpusys_top_adb_dcm_is_on()
52 ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
56 return ret; in dcm_mp_cpusys_top_adb_dcm_is_on()
98 bool ret = true; in dcm_mp_cpusys_top_apb_dcm_is_on() local
100 ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
103 ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
106 ret &= ((mmio_read_32(MP0_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
110 return ret; in dcm_mp_cpusys_top_apb_dcm_is_on()
[all …]
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| H A D | mtk_dcm.c | 36 bool ret = true; in check_dcm_state() local
38 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); in check_dcm_state()
39 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); in check_dcm_state()
40 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); in check_dcm_state()
42 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); in check_dcm_state()
43 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); in check_dcm_state()
44 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); in check_dcm_state()
45 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); in check_dcm_state()
46 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); in check_dcm_state()
47 ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); in check_dcm_state()
[all …]
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| /rk3399_ARM-atf/plat/socionext/uniphier/ |
| H A D | uniphier_io_storage.c | 198 int ret; in uniphier_io_block_setup() local
205 ret = mmap_add_dynamic_region(block_dev_spec->buffer.offset, in uniphier_io_block_setup()
209 if (ret) in uniphier_io_block_setup()
210 return ret; in uniphier_io_block_setup()
212 ret = register_io_dev_block(&uniphier_backend_dev_con); in uniphier_io_block_setup()
213 if (ret) in uniphier_io_block_setup()
214 return ret; in uniphier_io_block_setup()
222 int ret; in uniphier_io_memmap_setup() local
226 ret = mmap_add_dynamic_region(fip_offset, fip_offset, in uniphier_io_memmap_setup()
229 if (ret) in uniphier_io_memmap_setup()
[all …]
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| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/ |
| H A D | s32cc_clk_drv.c | 97 int ret = 0; in get_base_addr() local
132 ret = -EINVAL; in get_base_addr()
136 if (ret != 0) { in get_base_addr()
140 return ret; in get_base_addr()
173 int ret = 0; in enable_osc() local
175 ret = update_stack_depth(&ldepth); in enable_osc()
176 if (ret != 0) { in enable_osc()
177 return ret; in enable_osc()
191 ret = -EINVAL; in enable_osc()
195 return ret; in enable_osc()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/common/drivers/sdmmc/ |
| H A D | sdmmc.c | 44 int ret; in sdmmc_send_cmd() local
52 ret = ops->send_cmd(&cmd); in sdmmc_send_cmd()
54 if ((ret == 0) && (r_data != NULL)) { in sdmmc_send_cmd()
63 if (ret != 0) { in sdmmc_send_cmd()
64 VERBOSE("Send command %u error: %d\n", idx, ret); in sdmmc_send_cmd()
67 return ret; in sdmmc_send_cmd()
76 int ret; in sdmmc_device_state() local
84 ret = sdmmc_send_cmd(MMC_CMD(13), rca << RCA_SHIFT_OFFSET, in sdmmc_device_state()
86 if (ret != 0) { in sdmmc_device_state()
113 int ret; in sdmmc_write_blocks() local
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/ |
| H A D | apusys_ammu.c | 161 int ret = 0; in apummu_get_dns() local
164 ret = sec_get_dns(engine_type, sec_level, domain, ns); in apummu_get_dns()
165 if (ret) in apummu_get_dns()
172 return ret; in apummu_get_dns()
191 int i, ret; in apummu_add_apmcu_map() local
194 ret = apummu_get_dns(APUSYS_DEVICE_NUM, SEC_LEVEL_SECURE, &domain, &ns); in apummu_add_apmcu_map()
195 if (ret) { in apummu_add_apmcu_map()
196 return ret; in apummu_add_apmcu_map()
200 ret = apummu_add_map(APUMMU_APMCU_RSV_DESC_IDX, seg, seg0_input, seg0_output, 0, in apummu_add_apmcu_map()
203 if (ret) in apummu_add_apmcu_map()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dcm/ |
| H A D | mtk_dcm.c | 36 bool ret = true; in check_dcm_state() local
38 ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); in check_dcm_state()
39 ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); in check_dcm_state()
40 ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); in check_dcm_state()
42 ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); in check_dcm_state()
43 ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); in check_dcm_state()
44 ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); in check_dcm_state()
45 ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); in check_dcm_state()
46 ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); in check_dcm_state()
47 ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); in check_dcm_state()
[all …]
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| H A D | mtk_dcm_utils.c | 44 bool ret = true; in dcm_mp_cpusys_top_adb_dcm_is_on() local
46 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
49 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) & in dcm_mp_cpusys_top_adb_dcm_is_on()
52 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
56 return ret; in dcm_mp_cpusys_top_adb_dcm_is_on()
98 bool ret = true; in dcm_mp_cpusys_top_apb_dcm_is_on() local
100 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
103 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
106 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
110 return ret; in dcm_mp_cpusys_top_apb_dcm_is_on()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8173/ |
| H A D | plat_sip_calls.c | 45 uint32_t ret; in mt_sip_pwr_on_mtcmos() local
47 ret = mtcmos_non_cpu_ctrl(1, val); in mt_sip_pwr_on_mtcmos()
48 if (ret) in mt_sip_pwr_on_mtcmos()
56 uint32_t ret; in mt_sip_pwr_off_mtcmos() local
58 ret = mtcmos_non_cpu_ctrl(0, val); in mt_sip_pwr_off_mtcmos()
59 if (ret) in mt_sip_pwr_off_mtcmos()
79 uint64_t ret; in mediatek_plat_sip_handler() local
83 ret = mt_sip_pwr_on_mtcmos((uint32_t)x1); in mediatek_plat_sip_handler()
84 SMC_RET1(handle, ret); in mediatek_plat_sip_handler()
87 ret = mt_sip_pwr_off_mtcmos((uint32_t)x1); in mediatek_plat_sip_handler()
[all …]
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| /rk3399_ARM-atf/drivers/cfi/v2m/ |
| H A D | v2m_flash.c | 102 int ret; in nor_word_program() local
110 ret = nor_poll_dws(base_addr, DWS_WORD_PROGRAM_RETRIES); in nor_word_program()
111 if (ret == 0) { in nor_word_program()
118 ret = -EPERM; in nor_word_program()
122 if (ret == 0) in nor_word_program()
123 ret = nor_full_status_check(base_addr); in nor_word_program()
126 return ret; in nor_word_program()
137 int ret; in nor_erase() local
144 ret = nor_poll_dws(base_addr, DWS_WORD_ERASE_RETRIES); in nor_erase()
145 if (ret == 0) in nor_erase()
[all …]
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| /rk3399_ARM-atf/plat/imx/imx8m/ |
| H A D | imx8m_dyn_cfg_helpers.c | 25 int ret; in imx8m_event_log_fdt_init_overlay() local
29 ret = fdt_create_empty_tree(dtb, dt_size); in imx8m_event_log_fdt_init_overlay()
30 if (ret < 0) { in imx8m_event_log_fdt_init_overlay()
32 fdt_strerror(ret)); in imx8m_event_log_fdt_init_overlay()
33 return ret; in imx8m_event_log_fdt_init_overlay()
50 ret = fdt_setprop_string(dtb, offset, "target-path", "/"); in imx8m_event_log_fdt_init_overlay()
51 if (ret < 0) { in imx8m_event_log_fdt_init_overlay()
53 fdt_strerror(ret)); in imx8m_event_log_fdt_init_overlay()
54 return ret; in imx8m_event_log_fdt_init_overlay()
61 return ret; in imx8m_event_log_fdt_init_overlay()
[all …]
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| /rk3399_ARM-atf/plat/rpi/rpi3/ |
| H A D | rpi3_dyn_cfg_helpers.c | 20 int ret; in rpi3_event_log_fdt_init_overlay() local
24 ret = fdt_create_empty_tree(dtb, dt_size); in rpi3_event_log_fdt_init_overlay()
25 if (ret < 0) { in rpi3_event_log_fdt_init_overlay()
27 fdt_strerror(ret)); in rpi3_event_log_fdt_init_overlay()
28 return ret; in rpi3_event_log_fdt_init_overlay()
45 ret = fdt_setprop_string(dtb, offset, "target-path", "/"); in rpi3_event_log_fdt_init_overlay()
46 if (ret < 0) { in rpi3_event_log_fdt_init_overlay()
48 fdt_strerror(ret)); in rpi3_event_log_fdt_init_overlay()
49 return ret; in rpi3_event_log_fdt_init_overlay()
56 return ret; in rpi3_event_log_fdt_init_overlay()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/pmic_wrap/ |
| H A D | pmic_wrap_init_v3.c | 86 int32_t ret = 0x0; in pwrap_swinf_acc() local
113 ret = -E_PWR_NOT_INIT_DONE; in pwrap_swinf_acc()
118 ret = pwrap_check_idle((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta), in pwrap_swinf_acc()
120 if (ret != 0) { in pwrap_swinf_acc()
139 ret = -E_PWR_INVALID_ARG; in pwrap_swinf_acc()
145 ret = pwrap_check_vldclr((uintptr_t)(&mtk_pwrap->wacs[swinf_no].sta), TIMEOUT_READ); in pwrap_swinf_acc()
146 if (ret != 0) { in pwrap_swinf_acc()
159 if (ret < 0) in pwrap_swinf_acc()
160 ERROR("%s fail, ret=%d\n", __func__, ret); in pwrap_swinf_acc()
161 return ret; in pwrap_swinf_acc()
[all …]
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| /rk3399_ARM-atf/drivers/st/ddr/ |
| H A D | stm32mp2_ram.c | 30 int ret; in ddr_dt_get_ui_param() local
34 ret = fdt_read_uint32_array(fdt, node, "st,phy-basic", size, (uint32_t *)&config->uib); in ddr_dt_get_ui_param()
36 VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-basic", size, ret); in ddr_dt_get_ui_param()
37 if (ret != 0) { in ddr_dt_get_ui_param()
38 ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-basic", ret); in ddr_dt_get_ui_param()
43 ret = fdt_read_uint32_array(fdt, node, "st,phy-advanced", size, (uint32_t *)&config->uia); in ddr_dt_get_ui_param()
45 VERBOSE("%s: %s[0x%x] = %d\n", __func__, "st,phy-advanced", size, ret); in ddr_dt_get_ui_param()
46 if (ret != 0) { in ddr_dt_get_ui_param()
47 ERROR("%s: can't read %s, error=%d\n", __func__, "st,phy-advanced", ret); in ddr_dt_get_ui_param()
52 ret = fdt_read_uint32_array(fdt, node, "st,phy-mr", size, (uint32_t *)&config->uim); in ddr_dt_get_ui_param()
[all …]
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| /rk3399_ARM-atf/drivers/mentor/i2c/ |
| H A D | mi2cv.c | 275 int ret = 0; in mentor_i2c_probe() local
277 ret = mentor_i2c_start_bit_set(); in mentor_i2c_probe()
278 if (ret != 0) { in mentor_i2c_probe()
285 ret = mentor_i2c_address_set(chip, I2C_CMD_WRITE); in mentor_i2c_probe()
286 if (ret != 0) { in mentor_i2c_probe()
297 return ret; in mentor_i2c_probe()
409 static int mentor_i2c_unstuck(int ret) in mentor_i2c_unstuck() argument
413 if (ret != -ETIMEDOUT) in mentor_i2c_unstuck()
414 return ret; in mentor_i2c_unstuck()
424 ret = -EPERM; in mentor_i2c_unstuck()
[all …]
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| /rk3399_ARM-atf/plat/qti/common/src/ |
| H A D | qti_io_storage.c | 76 int ret; in qti_io_memmap_setup() local
78 ret = mmap_add_dynamic_region(qti_fip_spec.offset, qti_fip_spec.offset, in qti_io_memmap_setup()
80 if (ret) { in qti_io_memmap_setup()
81 return ret; in qti_io_memmap_setup()
84 ret = register_io_dev_memmap(&qti_backend_dev_con); in qti_io_memmap_setup()
85 if (ret) { in qti_io_memmap_setup()
86 return ret; in qti_io_memmap_setup()
94 int ret; in qti_io_fip_setup() local
96 ret = register_io_dev_fip(&qti_fip_dev_con); in qti_io_fip_setup()
97 if (ret) { in qti_io_fip_setup()
[all …]
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| /rk3399_ARM-atf/plat/allwinner/sun50i_a64/ |
| H A D | sunxi_power.c | 90 int ret; in rsb_init() local
92 ret = rsb_init_controller(); in rsb_init()
93 if (ret) in rsb_init()
94 return ret; in rsb_init()
97 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); in rsb_init()
98 if (ret) in rsb_init()
99 return ret; in rsb_init()
102 ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8); in rsb_init()
103 if (ret) in rsb_init()
104 return ret; in rsb_init()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/common/lpm_v2/ |
| H A D | mt_lp_api.c | 16 int ret, val; in mt_audio_update() local
23 ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_FMAUDIO, &val); in mt_audio_update()
29 ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_ADSP, &val); in mt_audio_update()
32 ret = -1; in mt_audio_update()
36 return ret; in mt_audio_update()
41 int ret, val; in mt_usb_update() local
47 ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_USB_INFRA, &val); in mt_usb_update()
53 ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_USB_HEADSET, &val); in mt_usb_update()
56 ret = -1; in mt_usb_update()
60 return ret; in mt_usb_update()
[all …]
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