Merge "feat(ti): de-assert AINACTS at boot" into integration

feat(ti): de-assert AINACTS at boot

De-asserting AINACTS at startup to enable ACP interface. This is
required to enable limited system level IO coherency via ACP port
(eg.: DMA traffic on AM62L driv

feat(ti): de-assert AINACTS at boot

De-asserting AINACTS at startup to enable ACP interface. This is
required to enable limited system level IO coherency via ACP port
(eg.: DMA traffic on AM62L driving ASEL = 14/15).

Change-Id: Iceaf992dec5dc37eae6dc06895585ea712f23496
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

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Merge changes from topic "ti-am62lxx-boot-notif" into integration

* changes:
feat(ti): am62lx init: boot notif and version msg
feat(ti): add support for boot notification msg
feat(ti): add mmu

Merge changes from topic "ti-am62lxx-boot-notif" into integration

* changes:
feat(ti): am62lx init: boot notif and version msg
feat(ti): add support for boot notification msg
feat(ti): add mmu regions for am62l soc
feat(ti): build generic timer

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feat(ti): am62lx init: boot notif and version msg

Consume the boot notification on this platform before we start further
communication with the system-firmware.

Change-Id: Ia9e5d8d616d7d9cd50ee5de2

feat(ti): am62lx init: boot notif and version msg

Consume the boot notification on this platform before we start further
communication with the system-firmware.

Change-Id: Ia9e5d8d616d7d9cd50ee5de2e4c8abe06104dc05
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(ti): add mmu regions for am62l soc

Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware b

feat(ti): add mmu regions for am62l soc

Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware blocks are accessible to the A53 cores on the
AM62L SoC.
Use 4K aligned address sizes wherever applicable, and update the
file header comment from "K3 SOC specific bl31_setup" to "k3low SoC
specific bl31_setup" to accurately represent the platform specific
nature of this file.
As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE
to WKUP_CTRL_MMR0_BASE to make name shorter.

Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(ti): build generic timer

Also, make sure we init the generic timer as part of the soc init
on am62lx as we use it later for delays

Change-Id: I921f4e4120ddaba588eb5b876231435fff3f7f3c
Signed-o

feat(ti): build generic timer

Also, make sure we init the generic timer as part of the soc init
on am62lx as we use it later for delays

Change-Id: I921f4e4120ddaba588eb5b876231435fff3f7f3c
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): ad

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): add support for TI mailbox driver
refactor(ti): move out k3/common to ti/common
refactor(ti): introduce ti_bl31_setup
refactor(ti): add the sec hdr to the ti sci msg
refactor(ti): rename the k3_sec_proxy_chan_id
refactor(ti): rename the sec_proxy functions
refactor(ti): add top level ti_sci transport layer
refactor(ti): move TI SCI and sec proxy to drivers

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feat(ti): introduce basic support for the AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development.

Some high

feat(ti): introduce basic support for the AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development.

Some highlights of AM62L SoC are:
- Single to Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem
- 16-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
- Multiple low power modes support, ex: Deep sleep and RTC+DDR
- Mailbox transport layer for TI SCI

For more information check out our Technical Reference Manual (TRM)
which is loacted here:

https://www.ti.com/lit/pdf/sprujb4

Change-Id: I9d7c707b5b220c5ec13bd2de67f872b3da3c308a
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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