1*43d7bbccSNina Wu /* 2*43d7bbccSNina Wu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*43d7bbccSNina Wu * 4*43d7bbccSNina Wu * SPDX-License-Identifier: BSD-3-Clause 5*43d7bbccSNina Wu */ 6*43d7bbccSNina Wu 7*43d7bbccSNina Wu #include <mtk_dcm.h> 8*43d7bbccSNina Wu #include <mtk_dcm_utils.h> 9*43d7bbccSNina Wu dcm_armcore(bool mode)10*43d7bbccSNina Wustatic void dcm_armcore(bool mode) 11*43d7bbccSNina Wu { 12*43d7bbccSNina Wu dcm_mp_cpusys_top_bus_pll_div_dcm(mode); 13*43d7bbccSNina Wu dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); 14*43d7bbccSNina Wu dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); 15*43d7bbccSNina Wu } 16*43d7bbccSNina Wu dcm_mcusys(bool on)17*43d7bbccSNina Wustatic void dcm_mcusys(bool on) 18*43d7bbccSNina Wu { 19*43d7bbccSNina Wu dcm_mp_cpusys_top_adb_dcm(on); 20*43d7bbccSNina Wu dcm_mp_cpusys_top_apb_dcm(on); 21*43d7bbccSNina Wu dcm_mp_cpusys_top_cpubiu_dcm(on); 22*43d7bbccSNina Wu dcm_mp_cpusys_top_misc_dcm(on); 23*43d7bbccSNina Wu dcm_mp_cpusys_top_mp0_qdcm(on); 24*43d7bbccSNina Wu dcm_cpccfg_reg_emi_wfifo(on); 25*43d7bbccSNina Wu dcm_mp_cpusys_top_last_cor_idle_dcm(on); 26*43d7bbccSNina Wu } 27*43d7bbccSNina Wu dcm_stall(bool on)28*43d7bbccSNina Wustatic void dcm_stall(bool on) 29*43d7bbccSNina Wu { 30*43d7bbccSNina Wu dcm_mp_cpusys_top_core_stall_dcm(on); 31*43d7bbccSNina Wu dcm_mp_cpusys_top_fcm_stall_dcm(on); 32*43d7bbccSNina Wu } 33*43d7bbccSNina Wu check_dcm_state(void)34*43d7bbccSNina Wustatic bool check_dcm_state(void) 35*43d7bbccSNina Wu { 36*43d7bbccSNina Wu bool ret = true; 37*43d7bbccSNina Wu 38*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); 39*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); 40*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); 41*43d7bbccSNina Wu 42*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); 43*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); 44*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); 45*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); 46*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); 47*43d7bbccSNina Wu ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); 48*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); 49*43d7bbccSNina Wu 50*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); 51*43d7bbccSNina Wu ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); 52*43d7bbccSNina Wu 53*43d7bbccSNina Wu return ret; 54*43d7bbccSNina Wu } 55*43d7bbccSNina Wu dcm_set_default(void)56*43d7bbccSNina Wubool dcm_set_default(void) 57*43d7bbccSNina Wu { 58*43d7bbccSNina Wu dcm_armcore(true); 59*43d7bbccSNina Wu dcm_mcusys(true); 60*43d7bbccSNina Wu dcm_stall(true); 61*43d7bbccSNina Wu 62*43d7bbccSNina Wu return check_dcm_state(); 63*43d7bbccSNina Wu } 64