1*49d3bd8cSGarmin Chang /* 2*49d3bd8cSGarmin Chang * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3*49d3bd8cSGarmin Chang * 4*49d3bd8cSGarmin Chang * SPDX-License-Identifier: BSD-3-Clause 5*49d3bd8cSGarmin Chang */ 6*49d3bd8cSGarmin Chang 7*49d3bd8cSGarmin Chang #include <mtk_dcm.h> 8*49d3bd8cSGarmin Chang #include <mtk_dcm_utils.h> 9*49d3bd8cSGarmin Chang dcm_armcore(bool mode)10*49d3bd8cSGarmin Changstatic void dcm_armcore(bool mode) 11*49d3bd8cSGarmin Chang { 12*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_bus_pll_div_dcm(mode); 13*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode); 14*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode); 15*49d3bd8cSGarmin Chang } 16*49d3bd8cSGarmin Chang dcm_mcusys(bool on)17*49d3bd8cSGarmin Changstatic void dcm_mcusys(bool on) 18*49d3bd8cSGarmin Chang { 19*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_adb_dcm(on); 20*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_apb_dcm(on); 21*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_cpubiu_dcm(on); 22*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_misc_dcm(on); 23*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_mp0_qdcm(on); 24*49d3bd8cSGarmin Chang dcm_cpccfg_reg_emi_wfifo(on); 25*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_last_cor_idle_dcm(on); 26*49d3bd8cSGarmin Chang } 27*49d3bd8cSGarmin Chang dcm_stall(bool on)28*49d3bd8cSGarmin Changstatic void dcm_stall(bool on) 29*49d3bd8cSGarmin Chang { 30*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_core_stall_dcm(on); 31*49d3bd8cSGarmin Chang dcm_mp_cpusys_top_fcm_stall_dcm(on); 32*49d3bd8cSGarmin Chang } 33*49d3bd8cSGarmin Chang check_dcm_state(void)34*49d3bd8cSGarmin Changstatic bool check_dcm_state(void) 35*49d3bd8cSGarmin Chang { 36*49d3bd8cSGarmin Chang bool ret = true; 37*49d3bd8cSGarmin Chang 38*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(); 39*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(); 40*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(); 41*49d3bd8cSGarmin Chang 42*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_adb_dcm_is_on(); 43*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_apb_dcm_is_on(); 44*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on(); 45*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_misc_dcm_is_on(); 46*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on(); 47*49d3bd8cSGarmin Chang ret &= dcm_cpccfg_reg_emi_wfifo_is_on(); 48*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(); 49*49d3bd8cSGarmin Chang 50*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on(); 51*49d3bd8cSGarmin Chang ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on(); 52*49d3bd8cSGarmin Chang 53*49d3bd8cSGarmin Chang return ret; 54*49d3bd8cSGarmin Chang } 55*49d3bd8cSGarmin Chang dcm_set_default(void)56*49d3bd8cSGarmin Changbool dcm_set_default(void) 57*49d3bd8cSGarmin Chang { 58*49d3bd8cSGarmin Chang dcm_armcore(true); 59*49d3bd8cSGarmin Chang dcm_mcusys(true); 60*49d3bd8cSGarmin Chang dcm_stall(true); 61*49d3bd8cSGarmin Chang 62*49d3bd8cSGarmin Chang return check_dcm_state(); 63*49d3bd8cSGarmin Chang } 64