| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | suspend.c | 191 uint32_t i, tmp; in data_training() local
219 for (i = 0; i < 4; i++) { in data_training()
220 if (!(rank_mask & (1 << i))) in data_training()
223 select_per_cs_training_index(ch, i); in data_training()
230 (0x1 << 16) | (i << 24)); in data_training()
263 for (i = 0; i < rank; i++) { in data_training()
264 select_per_cs_training_index(ch, i); in data_training()
270 (0x1 << 8) | (i << 16)); in data_training()
309 for (i = 0; i < rank; i++) { in data_training()
310 select_per_cs_training_index(ch, i); in data_training()
[all …]
|
| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/devapc/ |
| H A D | devapc.c | 181 int i; in dump_devapc() local
185 for (i = 0; i < 13; i++) { in dump_devapc()
189 i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + i * 4), in dump_devapc()
190 i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x100 + i * 4), in dump_devapc()
191 i, mmio_read_32(DEVAPC_INFRA_D0_APC_0 + 0x200 + i * 4)); in dump_devapc()
194 for (i = 0; i < 9; i++) { in dump_devapc()
198 i, mmio_read_32(DEVAPC_MM_D0_APC_0 + i * 4), in dump_devapc()
199 i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x100 + i * 4), in dump_devapc()
200 i, mmio_read_32(DEVAPC_MM_D0_APC_0 + 0x200 + i * 4)); in dump_devapc()
203 for (i = 0; i < 4; i++) { in dump_devapc()
[all …]
|
| /rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/ |
| H A D | regs.c | 30 static void cal_csn_config(int i, in cal_csn_config() argument
38 const unsigned int ap_n_en = popts->cs_odt[i].auto_precharge; in cal_csn_config()
39 const unsigned int odt_rd_cfg = popts->cs_odt[i].odt_rd_cfg; in cal_csn_config()
40 const unsigned int odt_wr_cfg = popts->cs_odt[i].odt_wr_cfg; in cal_csn_config()
46 if (i == 0) { in cal_csn_config()
59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) | in cal_csn_config()
69 debug("cs%d\n", i); in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
448 int i; in cal_ddr_sdram_cfg() local
470 for (i = 0; i < DDRC_NUM_CS; i++) { in cal_ddr_sdram_cfg()
[all …]
|
| /rk3399_ARM-atf/plat/arm/board/tc/ |
| H A D | rse_ap_tests.c | 34 size_t i; in run_tests() local
51 for (i = 0; i < ARRAY_SIZE(test_suites); ++i) { in run_tests()
52 struct test_suite_t *suite = &(test_suites[i]); in run_tests()
68 size_t i; in run_platform_tests() local
86 for (i = 0; i < ARRAY_SIZE(test_suites); ++i) { in run_platform_tests()
88 struct test_suite_t *suite = &(test_suites[i]); in run_platform_tests()
|
| /rk3399_ARM-atf/plat/xilinx/zynqmp/ |
| H A D | plat_psci.c | 80 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_off() local
82 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_off()
110 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_suspend() local
112 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_suspend()
131 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_on_finish() local
133 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_on_finish()
148 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in zynqmp_pwr_domain_suspend_finish() local
150 __func__, i, target_state->pwr_domain_state[i]); in zynqmp_pwr_domain_suspend_finish()
|
| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_psci.c | 104 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_off() local
106 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_off()
127 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_suspend() local
129 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_suspend()
144 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_on_finish() local
146 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_on_finish()
175 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_suspend_finish() local
177 __func__, i, target_state->pwr_domain_state[i]); in socfpga_pwr_domain_suspend_finish()
|
| /rk3399_ARM-atf/drivers/renesas/rcar/qos/H3/ |
| H A D | qos_init_h3_v11.c | 126 uint32_t i; in qos_init_h3_v11() local
128 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_h3_v11()
129 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_h3_v11()
130 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_h3_v11()
132 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_h3_v11()
133 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_h3_v11()
134 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_h3_v11()
|
| /rk3399_ARM-atf/drivers/nxp/csu/ |
| H A D | csu.c | 20 int i; in enable_layerscape_ns_access() local
22 for (i = 0; i < num; i++) { in enable_layerscape_ns_access()
23 reg = base + csu_ns_dev[i].ind / 2U; in enable_layerscape_ns_access()
25 if (csu_ns_dev[i].ind % 2U == 0U) { in enable_layerscape_ns_access()
27 val |= csu_ns_dev[i].val << 16U; in enable_layerscape_ns_access()
30 val |= csu_ns_dev[i].val; in enable_layerscape_ns_access()
|
| /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/ |
| H A D | apusys_rv_pwr_ctrl.h | 57 #define APU_MBOX(i) (APU_MBOX0 + 0x10000 * i) argument
59 #define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG) argument
60 #define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG) argument
61 #define APU_MBOX_WKUP_CFG(i) (APU_MBOX(i) + MBOX_WKUP_CFG) argument
81 #define APU_MBOX_OFFSET(i) (0x10000 * i) argument
|
| /rk3399_ARM-atf/drivers/arm/mhu/ |
| H A D | mhu_wrapper_v2_x.c | 92 uint32_t i; in clear_and_wait_for_next_signal() local
95 for (i = 0; i < num_channels; ++i) { in clear_and_wait_for_next_signal()
96 err = mhu_v2_x_channel_clear(dev, i); in clear_and_wait_for_next_signal()
120 uint32_t num_channels, i; in mhu_init_receiver() local
134 for (i = 0; i < (num_channels - 1); ++i) { in mhu_init_receiver()
135 err = mhu_v2_x_channel_mask_set(&MHU1_SEH_DEV, i, UINT32_MAX); in mhu_init_receiver()
169 uint32_t i; in mhu_send_data() local
190 for (i = 0; i < size; i += 4) { in mhu_send_data()
243 uint32_t i; in mhu_receive_data() local
274 for (i = 0; i < message_len; i += 4) { in mhu_receive_data()
[all …]
|
| /rk3399_ARM-atf/plat/mediatek/drivers/rng/mt8186/ |
| H A D | rng_plat.c | 87 for (int i = 0; i < ARRAY_SIZE(seed); i++) { in trng_prng() local
94 seed[i] = mmio_read_32(TRNG_DATA); in trng_prng()
107 for (int i = 0; i < ARRAY_SIZE(seed); i++) in trng_prng() local
108 rand[i] = seed[i]; in trng_prng()
125 for (int i = 0; i < num; i++) in get_true_rnd() local
126 val[i] = rand[i]; in get_true_rnd()
|
| /rk3399_ARM-atf/plat/rockchip/px30/drivers/secure/ |
| H A D | secure.h | 13 #define SGRF_SOC_CON(i) ((i) * 0x4) argument
14 #define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4) argument
28 #define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4) argument
29 #define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4) argument
|
| /rk3399_ARM-atf/drivers/brcm/spi/ |
| H A D | iproc_qspi.c | 175 uint32_t i; in mspi_xfer() local
186 for (i = 0; i < queues; i++) in mspi_xfer()
188 (i << 2), mode | CDRAM_CONT); in mspi_xfer()
191 for (i = 0; i < chunk; i++) in mspi_xfer()
195 (i << 2), tx[i]); in mspi_xfer()
204 for (i = 0; i < chunk; i++) { in mspi_xfer()
206 (i << 2), mode | CDRAM_CONT); in mspi_xfer()
210 (i << 3), tx[i]); in mspi_xfer()
253 for (i = 0; i < chunk; i++) { in mspi_xfer()
254 rx[i] = mmio_read_32(priv->mspi_hw + in mspi_xfer()
[all …]
|
| /rk3399_ARM-atf/drivers/nxp/sfp/ |
| H A D | fuse_prov.c | 46 int i; in write_fuses() local
49 for (i = 0; i < len; i++) { in write_fuses()
50 if (sfp_read32(&fuse_addr[i]) != 0) { in write_fuses()
56 for (i = 0; i < len; i++) { in write_fuses()
57 sfp_write32(&fuse_addr[i], fuse_hdr_val[i]); in write_fuses()
61 for (i = 0; i < len; i++) { in write_fuses()
62 if (sfp_read32(&fuse_addr[i]) != fuse_hdr_val[i]) { in write_fuses()
93 int i, ret = 0; in prog_oemuid() local
95 for (i = 0; i < 5; i++) { in prog_oemuid()
97 if (((fuse_hdr->flags >> (FLAG_OUID0_SHIFT + i)) & 0x1) != 0) { in prog_oemuid()
[all …]
|
| /rk3399_ARM-atf/plat/mediatek/drivers/ptp3/ |
| H A D | ptp3_common.c | 17 unsigned int i, addr, value; in ptp3_init() local
28 for (i = 0; i < NR_PTP3_CFG2_DATA; i++) { in ptp3_init()
29 addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); in ptp3_init()
30 value = ptp3_cfg2[i][PTP3_CFG_VALUE]; in ptp3_init()
35 for (i = 0; i < NR_PTP3_CFG2_DATA; i++) { in ptp3_init()
36 addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + PTP3_CORE_OFT(core); in ptp3_init()
38 if (i == 2) { in ptp3_init()
39 value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0; in ptp3_init()
41 value = ptp3_cfg2[i][PTP3_CFG_VALUE]; in ptp3_init()
|
| /rk3399_ARM-atf/lib/utils/ |
| H A D | mem_region.c | 33 size_t i; in clear_mem_regions() local
38 for (i = 0; i < nregions; i++) { in clear_mem_regions()
70 for (unsigned int i = 0U; i < nregions; i++) { in clear_map_dyn_mem_regions() local
71 begin = regions[i].base; in clear_map_dyn_mem_regions()
72 size = regions[i].nbytes; in clear_map_dyn_mem_regions()
119 size_t i; in mem_region_in_array_chk() local
127 for (i = 0U; i < nregions; i++) { in mem_region_in_array_chk()
|
| /rk3399_ARM-atf/plat/imx/imx93/ |
| H A D | trdc.c | 49 unsigned int i; in trdc_config() local
58 for (i = 0U; i < ARRAY_SIZE(trdc_mgr_blks); i++) { in trdc_config()
59 trdc_mgr_mbc_setup(&trdc_mgr_blks[i]); in trdc_config()
63 for (i = 0U; i < ARRAY_SIZE(trdc_cfg_info); i++) { in trdc_config()
64 trdc_setup(&trdc_cfg_info[i]); in trdc_config()
|
| /rk3399_ARM-atf/plat/intel/soc/common/lib/sha/ |
| H A D | sha.h | 21 #define GET_UINT64_BE(n, b, i) { \ argument
22 (n) = ((unsigned long long) (b)[(i)] << 56) |\
23 ((unsigned long long) (b)[(i) + 1] << 48) |\
24 ((unsigned long long) (b)[(i) + 2] << 40) |\
25 ((unsigned long long) (b)[(i) + 3] << 32) |\
26 ((unsigned long long) (b)[(i) + 4] << 24) |\
27 ((unsigned long long) (b)[(i) + 5] << 16) |\
28 ((unsigned long long) (b)[(i) + 6] << 8) |\
29 ((unsigned long long) (b)[(i) + 7]);\
32 #define PUT_UINT64_BE(n, b, i) { \ argument
[all …]
|
| /rk3399_ARM-atf/plat/qti/common/src/ |
| H A D | qti_syscall.c | 87 int i = 0; in qti_is_secure_io_access_allowed() local
89 for (i = 0; i < ARRAY_SIZE(qti_secure_io_allowed_regs); i++) { in qti_is_secure_io_access_allowed()
90 if ((uintptr_t) addr == qti_secure_io_allowed_regs[i]) { in qti_is_secure_io_access_allowed()
122 int i; in qti_mem_assign_validate_param() local
138 for (i = 0; i < u_num_mappings; i++) { in qti_mem_assign_validate_param()
139 if (((mem_info[i].mem_addr & (SIZE4K - 1)) != 0) in qti_mem_assign_validate_param()
140 || (mem_info[i].mem_size == 0) in qti_mem_assign_validate_param()
141 || ((mem_info[i].mem_size & (SIZE4K - 1)) != 0)) { in qti_mem_assign_validate_param()
143 (unsigned int)mem_info[i].mem_addr, in qti_mem_assign_validate_param()
144 (unsigned int)mem_info[i].mem_size); in qti_mem_assign_validate_param()
[all …]
|
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pwm/ |
| H A D | pwm.c | 29 uint32_t i, val; in disable_pwms() local
72 for (i = 0; i < 4; i++) { in disable_pwms()
73 val = mmio_read_32(PWM_BASE + PWM_CTRL(i)); in disable_pwms()
76 pwm_data.enable_bitmask |= (1 << i); in disable_pwms()
77 mmio_write_32(PWM_BASE + PWM_CTRL(i), val & ~PWM_ENABLE); in disable_pwms()
86 uint32_t i, val; in enable_pwms() local
88 for (i = 0; i < 4; i++) { in enable_pwms()
89 val = mmio_read_32(PWM_BASE + PWM_CTRL(i)); in enable_pwms()
90 if (!(pwm_data.enable_bitmask & (1 << i))) in enable_pwms()
92 mmio_write_32(PWM_BASE + PWM_CTRL(i), val | PWM_ENABLE); in enable_pwms()
|
| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/ |
| H A D | pmu.c | 112 int i; in dsu_restore_early() local
115 for (i = 0; i < DSUSGRF_SOC_CON_CNT; i++) in dsu_restore_early()
116 mmio_write_32(DSUSGRF_BASE + DSUSGRF_SOC_CON(i), in dsu_restore_early()
117 WITH_16BITS_WMSK(pmusram_data.dsusgrf_soc_con[i])); in dsu_restore_early()
119 for (i = 0; i < DSUSGRF_DDR_HASH_CON_CNT; i++) in dsu_restore_early()
120 mmio_write_32(DSUSGRF_BASE + DSUSGRF_DDR_HASH_CON(i), in dsu_restore_early()
121 pmusram_data.dsusgrf_ddr_hash_con[i]); in dsu_restore_early()
124 for (i = 0; i < FIREWALL_DSU_RGN_CNT; i++) in dsu_restore_early()
125 mmio_write_32(FIREWALL_DSU_BASE + FIREWALL_DSU_RGN(i), in dsu_restore_early()
126 pmusram_data.dsu_ddr_fw_rgn_reg[i]); in dsu_restore_early()
[all …]
|
| /rk3399_ARM-atf/plat/amd/versal2/ |
| H A D | plat_psci_pm.c | 69 size_t i; in versal2_pwr_domain_off() local
77 for (i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal2_pwr_domain_off()
79 __func__, i, target_state->pwr_domain_state[i]); in versal2_pwr_domain_off()
160 size_t i; in versal2_pwr_domain_suspend() local
168 for (i = 0; i <= PLAT_MAX_PWR_LVL; i in versal2_pwr_domain_suspend()
242 size_t i; versal2_pwr_domain_suspend_finish() local
347 uint64_t i; versal2_get_sys_suspend_power_state() local
[all...] |
| /rk3399_ARM-atf/drivers/marvell/ |
| H A D | trng.c | 62 uint8_t i; in mv_trng_get_random32() local
82 for (i = 0U; i < CP110_TRNG_MAX_RETRIES; i++) { in mv_trng_get_random32()
90 if (i == CP110_TRNG_MAX_RETRIES) { in mv_trng_get_random32()
94 for (i = 0U; i < num; i++) { in mv_trng_get_random32()
95 rand[i] = mmio_read_32(CP110_TRNG_OUTPUT_REG(i)); in mv_trng_get_random32()
|
| /rk3399_ARM-atf/plat/ti/common/ |
| H A D | k3_gicv3.c | 97 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { in k3_gic_save_context() local
98 gicv3_rdistif_save(i, &rdist_ctx[i]); in k3_gic_save_context()
106 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { in k3_gic_restore_context() local
107 gicv3_rdistif_init_restore(i, &rdist_ctx[i]); in k3_gic_restore_context()
|
| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | sunxi_scpi_pm.c | 152 unsigned int i; in sunxi_validate_power_state() local
165 for (i = 0; i <= power_level; ++i) { in sunxi_validate_power_state()
168 req_state->pwr_domain_state[i] = local_pstate; in sunxi_validate_power_state()
173 for (; i <= PLAT_MAX_PWR_LVL; ++i) { in sunxi_validate_power_state()
174 req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN; in sunxi_validate_power_state()
184 for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) { in sunxi_get_sys_suspend_power_state() local
185 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in sunxi_get_sys_suspend_power_state()
214 for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) { in sunxi_set_scpi_psci_ops() local
215 uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i); in sunxi_set_scpi_psci_ops()
|