Lines Matching refs:i
30 static void cal_csn_config(int i, in cal_csn_config() argument
38 const unsigned int ap_n_en = popts->cs_odt[i].auto_precharge; in cal_csn_config()
39 const unsigned int odt_rd_cfg = popts->cs_odt[i].odt_rd_cfg; in cal_csn_config()
40 const unsigned int odt_wr_cfg = popts->cs_odt[i].odt_wr_cfg; in cal_csn_config()
46 if (i == 0) { in cal_csn_config()
59 regs->cs[i].config = ((cs_n_en & 0x1) << 31) | in cal_csn_config()
69 debug("cs%d\n", i); in cal_csn_config()
70 debug(" _config = 0x%x\n", regs->cs[i].config); in cal_csn_config()
448 int i; in cal_ddr_sdram_cfg() local
470 for (i = 0; i < DDRC_NUM_CS; i++) { in cal_ddr_sdram_cfg()
471 if (popts->cs_odt[i].odt_rd_cfg != 0 || in cal_ddr_sdram_cfg()
472 popts->cs_odt[i].odt_wr_cfg != 0) { in cal_ddr_sdram_cfg()
532 int i; in cal_ddr_sdram_mode() local
716 for (i = 0; i < DDRC_NUM_CS; i++) { in cal_ddr_sdram_mode()
717 if (i != 0 && unq_mrs_en == 0) { in cal_ddr_sdram_mode()
725 rtt = popts->cs_odt[i].odt_rtt_norm; in cal_ddr_sdram_mode()
726 rtt_wr = popts->cs_odt[i].odt_rtt_wr; in cal_ddr_sdram_mode()
736 ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) != 0)) { in cal_ddr_sdram_mode()
754 switch (i) { in cal_ddr_sdram_mode()
890 int i; in cal_ddr_csn_bnds() local
894 for (i = 0; in cal_ddr_csn_bnds()
895 i < DDRC_NUM_CS && conf->cs_size[i]; in cal_ddr_csn_bnds()
896 i++) { in cal_ddr_csn_bnds()
899 sa = conf->cs_base_addr[i]; in cal_ddr_csn_bnds()
900 ea = sa + conf->cs_size[i] - 1; in cal_ddr_csn_bnds()
903 regs->cs[i].bnds = ((sa & 0xffff) << 16) | in cal_ddr_csn_bnds()
905 cal_csn_config(i, regs, popts, pdimm); in cal_ddr_csn_bnds()
908 regs->cs[i].bnds = 0xffffffff; in cal_ddr_csn_bnds()
911 debug("cs[%d].bnds = 0x%x\n", i, regs->cs[i].bnds); in cal_ddr_csn_bnds()
937 int i; in cal_ddr_addr_dec() local
984 for (i = 0; placement < cacheline; i++) { in cal_ddr_addr_dec()
985 map_col[i] = placement++; in cal_ddr_addr_dec()
988 for ( ; i < col_bits; i++) { in cal_ddr_addr_dec()
989 map_col[i] = placement++; in cal_ddr_addr_dec()
994 for ( ; i < 11; i++) { in cal_ddr_addr_dec()
995 map_col[i] = 0x3F; /* unused col bits */ in cal_ddr_addr_dec()
1012 for (i = 0; i < row_bits; i++) { in cal_ddr_addr_dec()
1013 map_row[i] = placement++; in cal_ddr_addr_dec()
1016 for ( ; i < 18; i++) { in cal_ddr_addr_dec()
1017 map_row[i] = 0x3F; /* unused row bits */ in cal_ddr_addr_dec()
1020 for (i = 39; i >= 0 ; i--) { in cal_ddr_addr_dec()
1021 if (i == intlv) { in cal_ddr_addr_dec()
1024 } else if (i < 3) { in cal_ddr_addr_dec()
1032 if (map_row[j] != i) { in cal_ddr_addr_dec()
1037 ERROR("%s wrong address bit %d\n", __func__, i); in cal_ddr_addr_dec()
1039 placement = i; in cal_ddr_addr_dec()
1043 if (map_col[j] != i) { in cal_ddr_addr_dec()
1048 ERROR("%s wrong address bit %d\n", __func__, i); in cal_ddr_addr_dec()
1050 placement = i; in cal_ddr_addr_dec()
1054 if (map_ba[j] != i) { in cal_ddr_addr_dec()
1059 ERROR("%s wrong address bit %d\n", __func__, i); in cal_ddr_addr_dec()
1061 placement = i; in cal_ddr_addr_dec()
1065 if (map_bg[j] != i) { in cal_ddr_addr_dec()
1070 ERROR("%s wrong address bit %d\n", __func__, i); in cal_ddr_addr_dec()
1072 placement = i; in cal_ddr_addr_dec()
1076 if (map_cs[j] != i) { in cal_ddr_addr_dec()
1081 ERROR("%s wrong address bit %d\n", __func__, i); in cal_ddr_addr_dec()
1083 placement = i; in cal_ddr_addr_dec()
1088 if ((i % 4) == 0) { in cal_ddr_addr_dec()
1139 for (i = 0; i < 10; i++) { in cal_ddr_addr_dec()
1140 debug("dec[%d] = 0x%x\n", i, regs->dec[i]); in cal_ddr_addr_dec()
1149 int i, j, k; in skip_caslat() local
1280 for (i = 0; i < size; i++) { in skip_caslat()
1281 if (bin[i].cl[0].tckmin_ps >= tckmin_ps) { in skip_caslat()
1285 if (i >= size) { in skip_caslat()
1289 if (bin[i].cl[0].tckmin_ps > tckmin_ps && i > 0) { in skip_caslat()
1290 i--; in skip_caslat()
1294 if ((bin[i].taamin_ps[j] == 0) || in skip_caslat()
1295 bin[i].taamin_ps[j] >= taamin_ps) { in skip_caslat()
1305 if (((bin[i].taamin_ps[j] == 0) && j > 0) || in skip_caslat()
1306 (bin[i].taamin_ps[j] > taamin_ps && j > 0)) { in skip_caslat()
1310 for (k = 0; bin[i].cl[k].tckmin_ps < mclk_ps && in skip_caslat()
1311 bin[i].cl[k].tckmin_ps < taamin_max; k++) in skip_caslat()
1313 if (bin[i].cl[k].tckmin_ps > mclk_ps && k > 0) { in skip_caslat()
1317 debug("Skip CL mask for this speed 0x%x\n", bin[i].cl[k].caslat[j]); in skip_caslat()
1319 return bin[i].cl[k].caslat[j]; in skip_caslat()
1333 int i; in compute_ddrc() local
1355 i = 24; in compute_ddrc()
1357 (i-- > 0)) { in compute_ddrc()
1361 if (i <= 0) { in compute_ddrc()