Searched hist:"3 dcb94dd847cf7a0c7d26772b2973e958ee079cc" (Results 1 – 7 of 7) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/stratix10/include/ |
| H A D | s10_memory_controller.h | 3dcb94dd847cf7a0c7d26772b2973e958ee079cc Mon Oct 21 08:35:08 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
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| H A D | s10_system_manager.h | 3dcb94dd847cf7a0c7d26772b2973e958ee079cc Mon Oct 21 08:35:08 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
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| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | agilex_memory_controller.h | 3dcb94dd847cf7a0c7d26772b2973e958ee079cc Mon Oct 21 08:35:08 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
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| H A D | agilex_system_manager.h | 3dcb94dd847cf7a0c7d26772b2973e958ee079cc Mon Oct 21 08:35:08 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
|
| /rk3399_ARM-atf/plat/intel/soc/stratix10/soc/ |
| H A D | s10_memory_controller.c | 3dcb94dd847cf7a0c7d26772b2973e958ee079cc Mon Oct 21 08:35:08 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
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| /rk3399_ARM-atf/plat/intel/soc/agilex/ |
| H A D | bl2_plat_setup.c | 3dcb94dd847cf7a0c7d26772b2973e958ee079cc Mon Oct 21 08:35:08 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/ |
| H A D | bl2_plat_setup.c | 3dcb94dd847cf7a0c7d26772b2973e958ee079cc Mon Oct 21 08:35:08 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
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