| #
8de2ae5f |
| 16-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): update outdated code for Linux direct boot" into integration
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| #
21a01dac |
| 04-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): update outdated code for Linux direct boot
1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status
Change-Id: I33905508aceb258ac8759c10079b2af977df
fix(intel): update outdated code for Linux direct boot
1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status
Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
b2534079 |
| 23-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "bridge-en" into integration
* changes:
intel: Add function to check fpga readiness
intel: Add bridge control for FPGA reconfig
intel: FPGA config_isdone() status quer
Merge changes from topic "bridge-en" into integration
* changes:
intel: Add function to check fpga readiness
intel: Add bridge control for FPGA reconfig
intel: FPGA config_isdone() status query
intel: System Manager refactoring
intel: Refactor reset manager driver
intel: Enable bridge access in Intel platform
intel: Modify non secure access function
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| #
3dcb94dd |
| 21-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi
intel: Enable bridge access in Intel platform
Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f
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| #
4244d0f3 |
| 13-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1819 from thloh85-intel/integration
plat: intel: Fix faulty DDR calibration value
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| #
51f366ac |
| 13-Feb-2019 |
Loh Tien Hock <tien.hock.loh@intel.com> |
plat: intel: Fix faulty DDR calibration value
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
M
plat: intel: Fix faulty DDR calibration value
A DDR calibration value is missing write mask, causing ECC DDR calibration
to fail. This patch addresses the issue. ECC should also be scrubbed before
MMU initializes, thus the scrubbing is moved to ddr intialization phase.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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| #
6ce30346 |
| 04-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1783 from thloh85-intel/integration_v2
plat: intel: Add BL2 support for Stratix 10 SoC
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| #
9d82ef26 |
| 04-Feb-2019 |
Loh Tien Hock <tien.hock.loh@intel.com> |
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scru
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
show more ...
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