Searched +full:tx +full:- +full:fifo +full:- +full:resize (Results 1 – 25 of 27) sorted by relevance
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1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Felipe Balbi <balbi@kernel.org>14 be presented as a standalone DT node with an optional vendor-specific18 - $ref: usb-drd.yaml#19 - if:25 - dr_mode29 $ref: usb-xhci.yaml#48 clock-names:[all …]
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a15";24 operating-points = <31 clock-names = "cpu";33 clock-latency = <300000>; /* From omap-cpufreq driver */36 cooling-min-level = <0>;37 cooling-max-level = <2>;38 #cooling-cells = <2>; /* min followed by max */[all …]
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)13 compatible = "socionext,uniphier-pxs3";14 #address-cells = <2>;15 #size-cells = <2>;16 interrupt-parent = <&gic>;19 #address-cells = <2>;20 #size-cells = <0>;22 cpu-map {41 compatible = "arm,cortex-a53", "arm,armv8";44 enable-method = "psci";[all …]
4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-pro4";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";23 enable-method = "psci";24 next-level-cache = <&l2>;[all …]
4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-pro5";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";24 enable-method = "psci";25 next-level-cache = <&l2>;[all …]
4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)11 compatible = "socionext,uniphier-pxs2";12 #address-cells = <1>;13 #size-cells = <1>;16 #address-cells = <1>;17 #size-cells = <0>;21 compatible = "arm,cortex-a9";24 enable-method = "psci";25 next-level-cache = <&l2>;[all …]
4 * Copyright (C) 2015-2016 Socionext Inc.7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)13 compatible = "socionext,uniphier-ld20";14 #address-cells = <2>;15 #size-cells = <2>;16 interrupt-parent = <&gic>;19 #address-cells = <2>;20 #size-cells = <0>;22 cpu-map {44 compatible = "arm,cortex-a72", "arm,armv8";[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/display/drm_mipi_dsi.h>7 #include <dt-bindings/input/input.h>11 compatible = "regulator-fixed";12 regulator-name = "vcc5v0_sys";13 regulator-always-on;14 regulator-boot-on;15 regulator-min-microvolt = <5000000>;16 regulator-max-microvolt = <5000000>;19 vdd_arm: vdd-arm {[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/rv1126-cru.h>7 #include <dt-bindings/power/rv1126-power.h>8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/interrupt-controller/irq.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/pinctrl/rockchip.h>12 #include <dt-bindings/soc/rockchip,boot-mode.h>13 #include <dt-bindings/soc/rockchip-system-status.h>14 #include <dt-bindings/suspend/rockchip-rv1126.h>[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */3 * core.h - DesignWare USB3 DRD Core Header5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com20 #include <linux/dma-mapping.h>192 /* Global Debug Queue/FIFO Space Available Register */222 /* Global TX Threshold Configuration Register for DWC_usb31 only */318 /* Global TX Fifo Size Register */324 /* Global RX Fifo Size Register */646 * struct dwc3_event_buffer - Software event buffer representation682 * struct dwc3_ep - device side endpoint representation[all …]
1 // SPDX-License-Identifier: GPL-2.03 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com20 #include <linux/dma-mapping.h>30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \31 & ~((d)->interval - 1))34 * dwc3_gadget_set_test_mode - enables usb2 test modes39 * success or -EINVAL if wrong Test Selector is passed.45 reg = dwc3_readl(dwc->regs, DWC3_DCTL); in dwc3_gadget_set_test_mode()57 return -EINVAL; in dwc3_gadget_set_test_mode()[all …]
1 // SPDX-License-Identifier: GPL-2.03 * core.c - DesignWare USB3 DRD Controller Core file5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com24 #include <linux/dma-mapping.h>44 * dwc3_get_dr_mode - Validates and sets dr_mode50 struct device *dev = dwc->dev; in dwc3_get_dr_mode()53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) in dwc3_get_dr_mode()54 dwc->dr_mode = USB_DR_MODE_OTG; in dwc3_get_dr_mode()56 mode = dwc->dr_mode; in dwc3_get_dr_mode()57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); in dwc3_get_dr_mode()[all …]
10 * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O12 * Copyright(c) 2002-2010 Exar Corp.16 #include <linux/io-64-nonatomic-lo-hi.h>20 #include "vxge-traffic.h"21 #include "vxge-config.h"22 #include "vxge-main.h"38 val64 = readq(&vp_reg->rxmac_vcfg0); in vxge_hw_vpath_set_zero_rx_frm_len()40 writeq(val64, &vp_reg->rxmac_vcfg0); in vxge_hw_vpath_set_zero_rx_frm_len()41 val64 = readq(&vp_reg->rxmac_vcfg0); in vxge_hw_vpath_set_zero_rx_frm_len()45 * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle[all …]
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */3 * Copyright (c) 2015-2017 QLogic Corporation4 * Copyright (c) 2019-2020 Marvell International Ltd.86 /* Light-L2 RX Producers in Tstorm RAM */94 /* LL2 TX Per Queue Stats */105 /* Light-L2 RX Producers in Tstorm RAM */282 /* Flags for Core TX BD */313 /* Core TX BD for Light L2 */326 /* Light L2 TX Destination */335 /* Ramrod data for tx queue start ramrod */[all …]
1 // SPDX-License-Identifier: GPL-2.02 /* Copyright (C) 2012-2020 B.A.T.M.A.N. contributors:4 * Martin Hundebøll, Jeppe Ledet-Pedersen7 #include "network-coding.h"42 #include "hard-interface.h"58 * batadv_nc_init() - one-time initialization for network coding74 * batadv_nc_start_timer() - initialise the nc periodic worker79 queue_delayed_work(batadv_event_workqueue, &bat_priv->nc.work, in batadv_nc_start_timer()84 * batadv_nc_tvlv_container_update() - update the network coding tvlv container92 nc_mode = atomic_read(&bat_priv->network_coding); in batadv_nc_tvlv_container_update()[all …]
1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)32 /* SGCR - Switch General Configuration Register33 * --------------------------------------------55 /* SPAD - Switch Physical Address Register56 * ---------------------------------------72 /* SMID - Switch Multicast ID73 * --------------------------[all …]
8 * Copyright (C) 1999-2017, Broadcom Corporation29 * <<Broadcom-WL-IPTag/Open:>>31 * $Id: dhd_msgbuf.c 701962 2017-05-30 06:13:15Z $117 #define MSGBUF_IOCTL_MAX_RQSTLEN (DHD_IOCTL_REQ_PKTBUFSZ - H2DRING_CTRL_SUB_ITEMSIZE)145 /* optimization to write "n" tx items at a time to ring */163 * 1. Dongle places a modulo-253 seqnum in last word of each D2H message214 * +----------------------------------------------------------------------------220 * the H2D common rings as well as the (N-BCMPCIE_H2D_COMMON_MSGRINGS) flowrings235 * H2D TxPost FLOWRING RingId = 5 + (N-1) FlowId = (N-1) (Nth flowring)255 * Likewise, in the D2H direction, the RingId - BCMPCIE_H2D_COMMON_MSGRINGS,[all …]
23 * <<Broadcom-WL-IPTag/Open:>>126 #define DHD_RDPTR_UPDATE_H2D_DB_MAGIC(ring) (0xDD000000 | (ring->idx << 16u) | ring->rd)128 #define DHD_WRPTR_UPDATE_H2D_DB_MAGIC(ring) (0xFF000000 | (ring->idx << 16u) | ring->wr)142 #define MSGBUF_IOCTL_MAX_RQSTLEN (DHD_IOCTL_REQ_PKTBUFSZ - H2DRING_CTRL_SUB_ITEMSIZE)146 * - as align bits: in DMA_ALLOC_CONSISTENT 1 << 4147 * - in ensuring that a buffer's va is 4 Byte aligned148 * - in rounding up a buffer length to 4 Bytes.179 /* optimization to write "n" tx items at a time to ring */220 * 1. Dongle places a modulo-253 seqnum in last word of each D2H message268 * +----------------------------------------------------------------------------[all …]
23 * <<Broadcom-WL-IPTag/Open:>>130 #define DHD_RDPTR_UPDATE_H2D_DB_MAGIC(ring) (0xDD000000 | (ring->idx << 16u) | ring->rd)132 #define DHD_WRPTR_UPDATE_H2D_DB_MAGIC(ring) (0xFF000000 | (ring->idx << 16u) | ring->wr)146 #define MSGBUF_IOCTL_MAX_RQSTLEN (DHD_IOCTL_REQ_PKTBUFSZ - H2DRING_CTRL_SUB_ITEMSIZE)150 * - as align bits: in DMA_ALLOC_CONSISTENT 1 << 4151 * - in ensuring that a buffer's va is 4 Byte aligned152 * - in rounding up a buffer length to 4 Bytes.183 /* optimization to write "n" tx items at a time to ring */224 * 1. Dongle places a modulo-253 seqnum in last word of each D2H message272 * +----------------------------------------------------------------------------[all …]
5 force -- enable ACPI if default was off6 on -- enable ACPI but allow fallback to DT [arm64]7 off -- disable ACPI if default was on8 noirq -- do not use ACPI for IRQ routing9 strict -- Be less tolerant of platforms that are not11 rsdt -- prefer RSDT over (default) XSDT12 copy_dsdt -- copy DSDT to memory26 If set to vendor, prefer vendor-specific driver58 Documentation/firmware-guide/acpi/debug.rst for more information about121 Disable auto-serialization of AML methods[all …]
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