1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 5*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 6*4882a593Smuzhiyun * published by the Free Software Foundation. 7*4882a593Smuzhiyun * Based on "omap4.dtsi" 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "dra7.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "ti,dra742", "ti,dra74", "ti,dra7"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpus { 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <0>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun cpu0: cpu@0 { 20*4882a593Smuzhiyun device_type = "cpu"; 21*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 22*4882a593Smuzhiyun reg = <0>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun operating-points = < 25*4882a593Smuzhiyun /* kHz uV */ 26*4882a593Smuzhiyun 1000000 1060000 27*4882a593Smuzhiyun 1176000 1160000 28*4882a593Smuzhiyun >; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks = <&dpll_mpu_ck>; 31*4882a593Smuzhiyun clock-names = "cpu"; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clock-latency = <300000>; /* From omap-cpufreq driver */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* cooling options */ 36*4882a593Smuzhiyun cooling-min-level = <0>; 37*4882a593Smuzhiyun cooling-max-level = <2>; 38*4882a593Smuzhiyun #cooling-cells = <2>; /* min followed by max */ 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun cpu@1 { 41*4882a593Smuzhiyun device_type = "cpu"; 42*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 43*4882a593Smuzhiyun reg = <1>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun pmu { 48*4882a593Smuzhiyun compatible = "arm,cortex-a15-pmu"; 49*4882a593Smuzhiyun interrupt-parent = <&wakeupgen>; 50*4882a593Smuzhiyun interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 51*4882a593Smuzhiyun <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ocp { 55*4882a593Smuzhiyun omap_dwc3_4: omap_dwc3_4@48940000 { 56*4882a593Smuzhiyun compatible = "ti,dwc3"; 57*4882a593Smuzhiyun ti,hwmods = "usb_otg_ss4"; 58*4882a593Smuzhiyun reg = <0x48940000 0x10000>; 59*4882a593Smuzhiyun interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <1>; 62*4882a593Smuzhiyun utmi-mode = <2>; 63*4882a593Smuzhiyun ranges; 64*4882a593Smuzhiyun status = "disabled"; 65*4882a593Smuzhiyun usb4: usb@48950000 { 66*4882a593Smuzhiyun compatible = "snps,dwc3"; 67*4882a593Smuzhiyun reg = <0x48950000 0x17000>; 68*4882a593Smuzhiyun interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 69*4882a593Smuzhiyun tx-fifo-resize; 70*4882a593Smuzhiyun maximum-speed = "high-speed"; 71*4882a593Smuzhiyun dr_mode = "otg"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun&dss { 78*4882a593Smuzhiyun reg = <0x58000000 0x80>, 79*4882a593Smuzhiyun <0x58004054 0x4>, 80*4882a593Smuzhiyun <0x58004300 0x20>, 81*4882a593Smuzhiyun <0x58005054 0x4>, 82*4882a593Smuzhiyun <0x58005300 0x20>; 83*4882a593Smuzhiyun reg-names = "dss", "pll1_clkctrl", "pll1", 84*4882a593Smuzhiyun "pll2_clkctrl", "pll2"; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun clocks = <&dss_dss_clk>, 87*4882a593Smuzhiyun <&dss_video1_clk>, 88*4882a593Smuzhiyun <&dss_video2_clk>; 89*4882a593Smuzhiyun clock-names = "fck", "video1_clk", "video2_clk"; 90*4882a593Smuzhiyun}; 91