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Searched full:timer0 (Results 1 – 25 of 172) sorted by relevance

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/OK3568_Linux_fs/u-boot/include/
H A Drk_timer_irq.h40 * Use timer0 and never change, because timer0 will be used in charge animation
42 * support timer0(not all timer) as wakeup source.
54 * Use timer0 and never change, because timer0 will be used in charge animation
56 * support timer0(not all timer) as wakeup source.
76 /* Only timer0 can wakeup system suspend */
80 /* Only timer0 can wakeup system suspend */
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dtimer.c13 static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE; variable
50 lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ); in timer_init()
51 lpc32xx_timer_count(timer0, 1); in timer_init()
58 return readl(&timer0->tc) - base; in get_timer()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/
H A Dezchip,nps400-timer0.txt5 - compatible : should be "ezchip,nps400-timer0"
7 Clocks required for compatible = "ezchip,nps400-timer0":
14 compatible = "ezchip,nps400-timer0";
H A Dsnps,arc-timer.txt4 - Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
17 timer0 {
H A Dactions,owl-timer.txt10 "timer0", "timer1", "timer2", "timer3"
20 interrupt-names = "timer0", "timer1";
H A Darm,sp804.yaml56 be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
91 timer0: timer@fc800000 {
H A Dingenic,tcu.yaml163 - const: timer0
270 clock-names = "timer0", "timer1", "timer2", "timer3",
/OK3568_Linux_fs/kernel/drivers/pinctrl/
H A Dpinctrl-lpc18xx.c168 [FUNC_TIMER0] = "timer0",
252 LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
253 LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
254 LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
255 LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
256 LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
257 LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
258 LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
260 LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
324 LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
[all …]
/OK3568_Linux_fs/kernel/arch/arc/boot/dts/
H A Dskeleton.dtsi30 /* TIMER0 with interrupt for clockevent */
31 timer0 {
H A Dskeleton_hs.dtsi25 /* TIMER0 with interrupt for clockevent */
26 timer0 {
H A Dskeleton_hs_idu.dtsi43 /* TIMER0 with interrupt for clockevent */
44 timer0 {
/OK3568_Linux_fs/u-boot/arch/nds32/dts/
H A Dag101p.dts17 tick-timer = &timer0;
51 timer0: timer@98400000 { label
H A Dae3xx.dts17 tick-timer = &timer0;
52 timer0: timer@f0400000 { label
/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Darc_timer.c7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
9 * We've designated TIMER0 for clockevents and TIMER1 for clocksource
270 .name = "ARC Timer0",
342 "Timer0 (per-cpu-tick)", evt); in arc_clockevent_setup()
H A Dtimer-nps.c205 .name = "NPS Timer0",
260 "Timer0 (per-cpu-tick)", in nps_setup_clockevent()
282 TIMER_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
H A DKconfig167 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
168 where TIMER0 serves as clockevent and TIMER1 serves as clocksource.
313 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
315 TIMER0 serves as clockevent while TIMER1 provides clocksource.
/OK3568_Linux_fs/kernel/arch/mips/loongson64/
H A Dhpet.c95 /* enables the timer0 to generate a periodic interrupt */ in hpet_set_state_periodic()
137 * set timer0 type in hpet_set_state_oneshot()
181 /* clear the TIMER0 irq status register */ in hpet_irq_handler()
/OK3568_Linux_fs/kernel/drivers/pci/hotplug/
H A Dcpcihp_zt5550.c113 * Disable timer0, timer1 and ENUM interrupts in zt5550_hc_config()
115 dbg("disabling timer0, timer1 and ENUM interrupts"); in zt5550_hc_config()
117 dbg("disabled timer0, timer1 and ENUM interrupts"); in zt5550_hc_config()
/OK3568_Linux_fs/kernel/drivers/clk/davinci/
H A Dpsc-dm646x.c31 LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
58 LPSC(34, 0, timer0, pll1_sysclk3, timer0_clkdev, LPSC_ALWAYS_ENABLED),
H A Dpsc-dm644x.c34 LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
56 LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
H A Dpsc-dm355.c35 LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
62 LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
H A Dpsc-dm365.c33 LPSC_CLKDEV1(timer0_clkdev, "timer0", NULL);
63 LPSC(27, 0, timer0, pll1_auxclk, timer0_clkdev, LPSC_ALWAYS_ENABLED),
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Daxm55xx.dtsi21 timer = &timer0;
147 timer0: timer@2010091000 { label
/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igc/
H A Digc_ptp.c161 * buffer. While two timestamps are available, one in timer0 reference and the
163 * timer0 reference.
176 * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH | in igc_ptp_rx_pktstamp()
/OK3568_Linux_fs/kernel/arch/arc/kernel/
H A Dsetup.c178 cpu->extn.timer0 = timer.t0; in read_arc_build_cfg_regs()
286 IS_AVAIL1(cpu->extn.timer0, "Timer0 "), in arc_cpu_mumbojumbo()
409 if (!cpu->extn.timer0) in arc_chk_core_config()
410 panic("Timer0 is not present!\n"); in arc_chk_core_config()

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