1*4882a593SmuzhiyunSynopsys ARC Local Timer with Interrupt Capabilities 2*4882a593Smuzhiyun- Found on all ARC CPUs (ARC700/ARCHS) 3*4882a593Smuzhiyun- Can be optionally programmed to interrupt on Limit 4*4882a593Smuzhiyun- Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically 5*4882a593Smuzhiyun TIMER0 used as clockevent provider (true for all ARC cores) 6*4882a593Smuzhiyun TIMER1 used for clocksource (mandatory for ARC700, optional for ARC HS) 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- compatible : should be "snps,arc-timer" 11*4882a593Smuzhiyun- interrupts : single Interrupt going into parent intc 12*4882a593Smuzhiyun (16 for ARCHS cores, 3 for ARC700 cores) 13*4882a593Smuzhiyun- clocks : phandle to the source clock 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun timer0 { 18*4882a593Smuzhiyun compatible = "snps,arc-timer"; 19*4882a593Smuzhiyun interrupts = <3>; 20*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 21*4882a593Smuzhiyun clocks = <&core_clk>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun timer1 { 25*4882a593Smuzhiyun compatible = "snps,arc-timer"; 26*4882a593Smuzhiyun clocks = <&core_clk>; 27*4882a593Smuzhiyun }; 28