1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/arch/cpu.h>
9*4882a593Smuzhiyun #include <asm/arch/clk.h>
10*4882a593Smuzhiyun #include <asm/arch/timer.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE;
14*4882a593Smuzhiyun static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE;
15*4882a593Smuzhiyun static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
16*4882a593Smuzhiyun
lpc32xx_timer_clock(u32 bit,int enable)17*4882a593Smuzhiyun static void lpc32xx_timer_clock(u32 bit, int enable)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun if (enable)
20*4882a593Smuzhiyun setbits_le32(&clk->timclk_ctrl1, bit);
21*4882a593Smuzhiyun else
22*4882a593Smuzhiyun clrbits_le32(&clk->timclk_ctrl1, bit);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
lpc32xx_timer_reset(struct timer_regs * timer,u32 freq)25*4882a593Smuzhiyun static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun writel(TIMER_TCR_COUNTER_RESET, &timer->tcr);
28*4882a593Smuzhiyun writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
29*4882a593Smuzhiyun writel(0, &timer->tc);
30*4882a593Smuzhiyun writel(0, &timer->pr);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Count mode is every rising PCLK edge */
33*4882a593Smuzhiyun writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Set prescale counter value */
36*4882a593Smuzhiyun writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
lpc32xx_timer_count(struct timer_regs * timer,int enable)39*4882a593Smuzhiyun static void lpc32xx_timer_count(struct timer_regs *timer, int enable)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun if (enable)
42*4882a593Smuzhiyun writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr);
43*4882a593Smuzhiyun else
44*4882a593Smuzhiyun writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
timer_init(void)47*4882a593Smuzhiyun int timer_init(void)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
50*4882a593Smuzhiyun lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
51*4882a593Smuzhiyun lpc32xx_timer_count(timer0, 1);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
get_timer(ulong base)56*4882a593Smuzhiyun ulong get_timer(ulong base)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun return readl(&timer0->tc) - base;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
__udelay(unsigned long usec)61*4882a593Smuzhiyun void __udelay(unsigned long usec)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
64*4882a593Smuzhiyun lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
65*4882a593Smuzhiyun lpc32xx_timer_count(timer1, 1);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun while (readl(&timer1->tc) < usec)
68*4882a593Smuzhiyun /* NOP */;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun lpc32xx_timer_count(timer1, 0);
71*4882a593Smuzhiyun lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
get_ticks(void)74*4882a593Smuzhiyun unsigned long long get_ticks(void)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun return get_timer(0);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
get_tbclk(void)79*4882a593Smuzhiyun ulong get_tbclk(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun return CONFIG_SYS_HZ;
82*4882a593Smuzhiyun }
83