1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/timer/arm,sp804.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ARM sp804 Dual Timers 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Haojian Zhuang <haojian.zhuang@linaro.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: |+ 13*4882a593Smuzhiyun The Arm SP804 IP implements two independent timers, configurable for 14*4882a593Smuzhiyun 16 or 32 bit operation and capable of running in one-shot, periodic, or 15*4882a593Smuzhiyun free-running mode. The input clock is shared, but can be gated and prescaled 16*4882a593Smuzhiyun independently for each timer. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon 19*4882a593Smuzhiyun SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804". 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun# Need a custom select here or 'arm,primecell' will match on lots of nodes 22*4882a593Smuzhiyunselect: 23*4882a593Smuzhiyun properties: 24*4882a593Smuzhiyun compatible: 25*4882a593Smuzhiyun contains: 26*4882a593Smuzhiyun oneOf: 27*4882a593Smuzhiyun - const: arm,sp804 28*4882a593Smuzhiyun - const: hisilicon,sp804 29*4882a593Smuzhiyun required: 30*4882a593Smuzhiyun - compatible 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunproperties: 33*4882a593Smuzhiyun compatible: 34*4882a593Smuzhiyun items: 35*4882a593Smuzhiyun - enum: 36*4882a593Smuzhiyun - arm,sp804 37*4882a593Smuzhiyun - hisilicon,sp804 38*4882a593Smuzhiyun - const: arm,primecell 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun interrupts: 41*4882a593Smuzhiyun description: | 42*4882a593Smuzhiyun If two interrupts are listed, those are the interrupts for timer 43*4882a593Smuzhiyun 1 and 2, respectively. If there is only a single interrupt, it is 44*4882a593Smuzhiyun either a combined interrupt or the sole interrupt of one timer, as 45*4882a593Smuzhiyun specified by the "arm,sp804-has-irq" property. 46*4882a593Smuzhiyun minItems: 1 47*4882a593Smuzhiyun maxItems: 2 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun reg: 50*4882a593Smuzhiyun description: The physical base address of the SP804 IP. 51*4882a593Smuzhiyun maxItems: 1 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun clocks: 54*4882a593Smuzhiyun description: | 55*4882a593Smuzhiyun Clocks driving the dual timer hardware. This list should 56*4882a593Smuzhiyun be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1 57*4882a593Smuzhiyun clock, apb_pclk. A single clock can also be specified if the same 58*4882a593Smuzhiyun clock is used for all clock inputs. 59*4882a593Smuzhiyun oneOf: 60*4882a593Smuzhiyun - items: 61*4882a593Smuzhiyun - description: clock for timer 1 62*4882a593Smuzhiyun - description: clock for timer 2 63*4882a593Smuzhiyun - description: bus clock 64*4882a593Smuzhiyun - items: 65*4882a593Smuzhiyun - description: unified clock for both timers and the bus 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun clock-names: true 68*4882a593Smuzhiyun # The original binding did not specify any clock names, and there is no 69*4882a593Smuzhiyun # consistent naming used in the existing DTs. The primecell binding 70*4882a593Smuzhiyun # requires the "apb_pclk" name, so we need this property. 71*4882a593Smuzhiyun # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs. 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun arm,sp804-has-irq: 74*4882a593Smuzhiyun description: If only one interrupt line is connected to the interrupt 75*4882a593Smuzhiyun controller, this property specifies which timer is connected to this 76*4882a593Smuzhiyun line. 77*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 78*4882a593Smuzhiyun minimum: 1 79*4882a593Smuzhiyun maximum: 2 80*4882a593Smuzhiyun 81*4882a593Smuzhiyunrequired: 82*4882a593Smuzhiyun - compatible 83*4882a593Smuzhiyun - interrupts 84*4882a593Smuzhiyun - reg 85*4882a593Smuzhiyun - clocks 86*4882a593Smuzhiyun 87*4882a593SmuzhiyunadditionalProperties: false 88*4882a593Smuzhiyun 89*4882a593Smuzhiyunexamples: 90*4882a593Smuzhiyun - | 91*4882a593Smuzhiyun timer0: timer@fc800000 { 92*4882a593Smuzhiyun compatible = "arm,sp804", "arm,primecell"; 93*4882a593Smuzhiyun reg = <0xfc800000 0x1000>; 94*4882a593Smuzhiyun interrupts = <0 0 4>, <0 1 4>; 95*4882a593Smuzhiyun clocks = <&timclk1>, <&timclk2>, <&pclk>; 96*4882a593Smuzhiyun clock-names = "timer1", "timer2", "apb_pclk"; 97*4882a593Smuzhiyun }; 98