1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun/ { 3*4882a593Smuzhiyun compatible = "nds32 ae3xx"; 4*4882a593Smuzhiyun #address-cells = <1>; 5*4882a593Smuzhiyun #size-cells = <1>; 6*4882a593Smuzhiyun interrupt-parent = <&intc>; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun aliases { 9*4882a593Smuzhiyun uart0 = &serial0; 10*4882a593Smuzhiyun ethernet0 = &mac0; 11*4882a593Smuzhiyun } ; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */ 15*4882a593Smuzhiyun bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; 16*4882a593Smuzhiyun stdout-path = "uart0:38400n8"; 17*4882a593Smuzhiyun tick-timer = &timer0; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun memory@0 { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cpus { 26*4882a593Smuzhiyun #address-cells = <1>; 27*4882a593Smuzhiyun #size-cells = <0>; 28*4882a593Smuzhiyun cpu@0 { 29*4882a593Smuzhiyun compatible = "andestech,n13"; 30*4882a593Smuzhiyun reg = <0>; 31*4882a593Smuzhiyun /* FIXME: to fill correct frqeuency */ 32*4882a593Smuzhiyun clock-frequency = <60000000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun intc: interrupt-controller { 37*4882a593Smuzhiyun compatible = "andestech,atnointc010"; 38*4882a593Smuzhiyun #interrupt-cells = <1>; 39*4882a593Smuzhiyun interrupt-controller; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun serial0: serial@f0300000 { 43*4882a593Smuzhiyun compatible = "andestech,uart16550", "ns16550a"; 44*4882a593Smuzhiyun reg = <0xf0300000 0x1000>; 45*4882a593Smuzhiyun interrupts = <7 4>; 46*4882a593Smuzhiyun clock-frequency = <14745600>; 47*4882a593Smuzhiyun reg-shift = <2>; 48*4882a593Smuzhiyun reg-offset = <32>; 49*4882a593Smuzhiyun no-loopback-test = <1>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun timer0: timer@f0400000 { 53*4882a593Smuzhiyun compatible = "andestech,atcpit100"; 54*4882a593Smuzhiyun reg = <0xf0400000 0x1000>; 55*4882a593Smuzhiyun interrupts = <2 4>; 56*4882a593Smuzhiyun clock-frequency = <30000000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun mac0: mac@e0100000 { 60*4882a593Smuzhiyun compatible = "andestech,atmac100"; 61*4882a593Smuzhiyun reg = <0xe0100000 0x1000>; 62*4882a593Smuzhiyun interrupts = <25 4>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun nor@0,0 { 66*4882a593Smuzhiyun compatible = "cfi-flash"; 67*4882a593Smuzhiyun reg = <0x88000000 0x1000>; 68*4882a593Smuzhiyun bank-width = <2>; 69*4882a593Smuzhiyun device-width = <1>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun}; 73