Searched +full:tegra210 +full:- +full:emc (Results 1 – 18 of 18) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.02 tegra-mc-y := mc.o4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include "tegra210-emc.h"15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local19 timings = memremap(rmem->base, rmem->size, MEMREMAP_WB); in tegra210_emc_table_device_init()21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()22 return -ENOMEM; in tegra210_emc_table_device_init()35 if (emc->derated) { in tegra210_emc_table_device_init()36 dev_warn(dev, "excess EMC table '%s'\n", rmem->name); in tegra210_emc_table_device_init()40 if (emc->nominal) { in tegra210_emc_table_device_init()41 if (count != emc->num_timings) { in tegra210_emc_table_device_init()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only15 This driver is for the External Memory Controller (EMC) found on16 Tegra20 chips. The EMC controls the external DRAM on the board.25 This driver is for the External Memory Controller (EMC) found on26 Tegra30 chips. The EMC controls the external DRAM on the board.35 This driver is for the External Memory Controller (EMC) found on36 Tegra124 chips. The EMC controls the external DRAM on the board.45 tristate "NVIDIA Tegra210 External Memory Controller driver"49 This driver is for the External Memory Controller (EMC) found on50 Tegra210 chips. The EMC controls the external DRAM on the board.
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.21 #include "tegra210-emc.h"22 #include "tegra210-mc.h"62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \69 next->trim_perch_regs[EMC ## chan ## \561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local564 if (!emc->last) in tegra210_emc_train()567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.14 #include "tegra210-emc.h"15 #include "tegra210-mc.h"36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument53 * PTFV defines - basically just indexes into the per table PTFV array.78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })86 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.891 /* nominal EMC frequency table */893 /* derated EMC frequency table */939 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);940 u32 (*periodic_compensation)(struct tegra210_emc *emc);943 static inline void emc_writel(struct tegra210_emc *emc, u32 value, in emc_writel() argument946 writel_relaxed(value, emc->regs + offset); in emc_writel()949 static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset) in emc_readl() argument951 return readl_relaxed(emc->regs + offset); in emc_readl()[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra210 SoC External Memory Controller10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>14 The EMC interfaces with the off-chip SDRAM to service the request stream19 const: nvidia,tegra210-emc26 - description: external memory clock[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra194-clock.h>3 #include <dt-bindings/gpio/tegra194-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>7 #include <dt-bindings/power/tegra194-powergate.h>8 #include <dt-bindings/reset/tegra194-reset.h>9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>10 #include <dt-bindings/memory/tegra194-mc.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra210-car.h>3 #include <dt-bindings/gpio/tegra-gpio.h>4 #include <dt-bindings/memory/tegra210-mc.h>5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>7 #include <dt-bindings/reset/tegra210-car.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/thermal/tegra124-soctherm.h>10 #include <dt-bindings/soc/tegra-pmc.h>[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-y += clk.o3 obj-y += clk-audio-sync.o4 obj-y += clk-dfll.o5 obj-y += clk-divider.o6 obj-y += clk-periph.o7 obj-y += clk-periph-fixed.o8 obj-y += clk-periph-gate.o9 obj-y += clk-pll.o10 obj-y += clk-pll-out.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.8 #include <linux/clk-provider.h>17 #include <dt-bindings/clock/tegra210-car.h>18 #include <dt-bindings/reset/tegra210-car.h>23 #include "clk-id.h"27 * banks present in the Tegra210 CAR IP block. The banks are264 * SDM fractional divisor is 16-bit 2's complement signed number within265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to[all …]
1 // SPDX-License-Identifier: GPL-2.0-only7 #include <linux/clk-provider.h>16 #include "clk-id.h"130 #define MASK(x) (BIT(x) - 1)781 * Critical for RAM re-repair operation, which must occur on resume791 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),804 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),877 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()881 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()885 data->periph.gate.regs = bank; in periph_clk_init()[all …]
2 # (C) Copyright 2010-2015 Nvidia Corporation.4 # (C) Copyright 2000-20087 # SPDX-License-Identifier: GPL-2.0+12 obj-y += spl.o13 obj-y += cpu.o15 obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o18 obj-y += ap.o19 obj-y += board.o board2.o20 obj-y += cache.o21 obj-y += clock.o[all …]
2 * (C) Copyright 2010-20155 * SPDX-License-Identifier: GPL-2.0+17 #include <asm/arch-tegra/ap.h>18 #include <asm/arch-tegra/board.h>19 #include <asm/arch-tegra/pmc.h>20 #include <asm/arch-tegra/sys_proto.h>21 #include <asm/arch-tegra/warmboot.h>59 * This register reads 0xffffffff in non-secure mode. This register in tegra_cpu_is_non_secure()62 * non-secure mode. in tegra_cpu_is_non_secure()65 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0); in tegra_cpu_is_non_secure()[all …]
3 * SPDX-License-Identifier: GPL-2.0+29 * good reason why driver-model conversion is infeasible. Examples include35 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),36 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),37 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),38 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),39 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),41 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),42 COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),43 COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"),[all …]
1 // SPDX-License-Identifier: GPL-2.011 #include <linux/dma-mapping.h>280 return readl(tegra->fpci_base + offset); in fpci_readl()286 writel(value, tegra->fpci_base + offset); in fpci_writel()291 return readl(tegra->ipfs_base + offset); in ipfs_readl()297 writel(value, tegra->ipfs_base + offset); in ipfs_writel()324 struct clk *clk = tegra->ss_src_clk; in tegra_xusb_set_ss_clk()338 new_parent_rate = clk_get_rate(tegra->pll_u_480m); in tegra_xusb_set_ss_clk()345 err = clk_set_parent(clk, tegra->pll_u_480m); in tegra_xusb_set_ss_clk()361 err = clk_set_parent(clk, tegra->clk_m); in tegra_xusb_set_ss_clk()[all …]
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