1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: NVIDIA Tegra210 SoC External Memory Controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Thierry Reding <thierry.reding@gmail.com>
11*4882a593Smuzhiyun  - Jon Hunter <jonathanh@nvidia.com>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription: |
14*4882a593Smuzhiyun  The EMC interfaces with the off-chip SDRAM to service the request stream
15*4882a593Smuzhiyun  sent from the memory controller.
16*4882a593Smuzhiyun
17*4882a593Smuzhiyunproperties:
18*4882a593Smuzhiyun  compatible:
19*4882a593Smuzhiyun    const: nvidia,tegra210-emc
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  reg:
22*4882a593Smuzhiyun    maxItems: 3
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun  clocks:
25*4882a593Smuzhiyun    items:
26*4882a593Smuzhiyun      - description: external memory clock
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  clock-names:
29*4882a593Smuzhiyun    items:
30*4882a593Smuzhiyun      - const: emc
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  interrupts:
33*4882a593Smuzhiyun    items:
34*4882a593Smuzhiyun      - description: EMC general interrupt
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun  memory-region:
37*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle
38*4882a593Smuzhiyun    description:
39*4882a593Smuzhiyun      phandle to a reserved memory region describing the table of EMC
40*4882a593Smuzhiyun      frequencies trained by the firmware
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  nvidia,memory-controller:
43*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/phandle
44*4882a593Smuzhiyun    description:
45*4882a593Smuzhiyun      phandle of the memory controller node
46*4882a593Smuzhiyun
47*4882a593Smuzhiyunrequired:
48*4882a593Smuzhiyun  - compatible
49*4882a593Smuzhiyun  - reg
50*4882a593Smuzhiyun  - clocks
51*4882a593Smuzhiyun  - clock-names
52*4882a593Smuzhiyun  - nvidia,memory-controller
53*4882a593Smuzhiyun
54*4882a593SmuzhiyunadditionalProperties: false
55*4882a593Smuzhiyun
56*4882a593Smuzhiyunexamples:
57*4882a593Smuzhiyun  - |
58*4882a593Smuzhiyun    #include <dt-bindings/clock/tegra210-car.h>
59*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun    reserved-memory {
62*4882a593Smuzhiyun        #address-cells = <1>;
63*4882a593Smuzhiyun        #size-cells = <1>;
64*4882a593Smuzhiyun        ranges;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun        emc_table: emc-table@83400000 {
67*4882a593Smuzhiyun            compatible = "nvidia,tegra210-emc-table";
68*4882a593Smuzhiyun            reg = <0x83400000 0x10000>;
69*4882a593Smuzhiyun        };
70*4882a593Smuzhiyun    };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun    external-memory-controller@7001b000 {
73*4882a593Smuzhiyun        compatible = "nvidia,tegra210-emc";
74*4882a593Smuzhiyun        reg = <0x7001b000 0x1000>,
75*4882a593Smuzhiyun              <0x7001e000 0x1000>,
76*4882a593Smuzhiyun              <0x7001f000 0x1000>;
77*4882a593Smuzhiyun        clocks = <&tegra_car TEGRA210_CLK_EMC>;
78*4882a593Smuzhiyun        clock-names = "emc";
79*4882a593Smuzhiyun        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
80*4882a593Smuzhiyun        memory-region = <&emc_table>;
81*4882a593Smuzhiyun        nvidia,memory-controller = <&mc>;
82*4882a593Smuzhiyun    };
83