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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock DT bindings
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
18 - enum:
19 - ingenic,jz4740-rtc
20 - ingenic,jz4760-rtc
21 - items:
[all …]
/OK3568_Linux_fs/kernel/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
66 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
76 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); in jz4740_rtc_wait_write_ready()
78 return timeout ? 0 : -EIO; in jz4740_rtc_wait_write_ready()
90 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
93 ctrl = readl(rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
94 } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout); in jz4780_rtc_enable_write()
96 return timeout ? 0 : -EIO; in jz4780_rtc_enable_write()
104 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
17 waits for this period of time before starting the
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
14 pp1250_s3: pp1250-s3 {
15 compatible = "regulator-fixed";
16 regulator-name = "pp1250_s3";
19 regulator-always-on;
20 regulator-boot-on;
21 regulator-min-microvolt = <1250000>;
22 regulator-max-microvolt = <1250000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/pps/clients/
H A Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
19 #include <linux/pps-gpio.h>
34 struct timer_list echo_timer; /* timer to reset echo active state */
51 /* Get the time stamp first */ in pps_gpio_irq_handler()
56 rising_edge = gpiod_get_value(info->gpio_pin); in pps_gpio_irq_handler()
57 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
58 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
59 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
[all …]
/OK3568_Linux_fs/kernel/arch/mips/include/asm/sn/
H A Dioc3.h1 /* SPDX-License-Identifier: GPL-2.0 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
153 u32 pad1[(0x20000 - 0x00154) / 4];
157 u32 pad2[(0x40000 - 0x20180) / 4];
160 u32 ssram[(0x80000 - 0x40000) / 4];
163 0x80000 - Access to the generic devices selected with DEV0
165 0xA0000 - Access to the generic devices selected with DEV1
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c1 // SPDX-License-Identifier: GPL-2.0-only
69 struct i2c_adapter *adap = client->adapter; in ps8622_set()
73 msg.addr = client->addr + page; in ps8622_set()
81 client->addr + page, reg, val, ret); in ps8622_set()
87 struct i2c_client *cl = ps8622->client; in ps8622_send_config()
138 /* [7:5] DCO_FTRNG=+-40% */ in ps8622_send_config()
148 /* Gitune=-37% */ in ps8622_send_config()
168 /* [7:6] Right-bar GPIO output strength is 8mA */ in ps8622_send_config()
180 err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count); in ps8622_send_config()
185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/nxp/
H A DREADME_MLAN4 Copyright 2008-2022 NXP
31 uap_oper_ctrl: uAP operation control when in-STA disconnect with ext-AP
33 For example, to install multi-chip driver,
36 …wifi_mod_para.conf is used to support multi-chips which has different load module parameters. It c…
107 pcie_int_mode=0|1|2 <Legacy mode, MSI mode (default), MSI-X mode>
114 expected PA current is expected to be in the 80-90 mA range for b/g/n modes
115 wakelock_timeout=<set wakelock_timeout value (ms)>
118 level(0/1) for normal wakeup; low four bits Y: GPIO pin number. This parameter
122 …hs_mimo_switch=0|1 <Disable dynamic MIMO-SISO switch during host sleep (default) | Enable dynamic …
126 GoAgeoutTime=0|x <use default ageout time (default) | set Go age out time xTU(TU 100ms)>
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb/
H A Dpm3393.c7 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
96 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
102 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
106 /* Port reset. */
124 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
147 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
153 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_enable()
154 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
156 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
44 #define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */
45 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
49 /* Physical Func Reset Done Indication */
62 /* Interrupt acknowledge Auto-mask */
91 #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
183 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
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/OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/ixgb/
H A Dixgb_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2008 Intel Corporation. */
61 /* Workaround for 82597EX reset errata */ in ixgb_mac_reset()
67 /* Delay a few ms just to allow the reset to complete */ in ixgb_mac_reset()
71 /* Make sure the self-clearing global reset bit did self clear */ in ixgb_mac_reset()
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); in ixgb_mac_reset()
75 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) { in ixgb_mac_reset()
86 if (hw->phy_type == ixgb_phy_type_txn17401) in ixgb_mac_reset()
93 * Reset the transmit and receive units; mask and clear all interrupts.
95 * hw - Struct containing variables accessed by shared code
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/
H A Dsiutils.c2 * Misc utility routines for accessing chip-specific features
3 * of the SiliconBackplane-based Broadcom chips.
22 * <<Broadcom-WL-IPTag/Dual:>>
116 * the write. During that time the 'SlowWritePending' bit in the PMUStatus register is set.
166 static void si_gci_get_chipctrlreg_ringidx_base4(uint32 pin, uint32 *regidx, uint32 *pos);
167 static uint8 si_gci_get_chipctrlreg_ringidx_base8(uint32 pin, uint32 *regidx, uint32 *pos);
193 /* global variable to indicate GCI reset is done */
226 static uint32 wd_msticks; /**< watchdog timer ticks normalized to ms */
264 * devid - pci device id (used to determine chip#)
265 * osh - opaque OS handle
[all …]
H A Dbcmutils.c2 * Driver O/S-independent utility routines
21 * <<Broadcom-WL-IPTag/Dual:>>
46 #ifndef ASSERT
47 #define ASSERT(exp) macro
58 #ifdef ASSERT
59 #undef ASSERT
60 #endif /* ASSERT */
61 #define ASSERT(exp) macro
94 0, 0, 0, 0, 0, 0, 0, 0, /* BK->BE */
260 /* Read an array of values from a possibly slice-specific nvram string
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/
H A Dsiutils.c2 * Misc utility routines for accessing chip-specific features
3 * of the SiliconBackplane-based Broadcom chips.
22 * <<Broadcom-WL-IPTag/Dual:>>
116 * the write. During that time the 'SlowWritePending' bit in the PMUStatus register is set.
166 static void si_gci_get_chipctrlreg_ringidx_base4(uint32 pin, uint32 *regidx, uint32 *pos);
167 static uint8 si_gci_get_chipctrlreg_ringidx_base8(uint32 pin, uint32 *regidx, uint32 *pos);
193 /* global variable to indicate GCI reset is done */
226 static uint32 wd_msticks; /**< watchdog timer ticks normalized to ms */
264 * devid - pci device id (used to determine chip#)
265 * osh - opaque OS handle
[all …]
H A Dbcmutils.c2 * Driver O/S-independent utility routines
21 * <<Broadcom-WL-IPTag/Dual:>>
46 #ifndef ASSERT
47 #define ASSERT(exp) macro
58 #ifdef ASSERT
59 #undef ASSERT
60 #endif /* ASSERT */
61 #define ASSERT(exp) macro
94 0, 0, 0, 0, 0, 0, 0, 0, /* BK->BE */
260 /* Read an array of values from a possibly slice-specific nvram string
[all …]
/OK3568_Linux_fs/kernel/drivers/macintosh/
H A Dvia-cuda.c1 // SPDX-License-Identifier: GPL-2.0
7 * This MCU controls system power, Parameter RAM, Real Time Clock and the
35 /* VIA registers - spaced 0x200 bytes apart */
37 #define B 0 /* B-side data */
38 #define A RS /* A-side data */
39 #define DIRB (2*RS) /* B-side direction (1=output) */
40 #define DIRA (3*RS) /* A-side direction (1=output) */
52 #define ANH (15*RS) /* A-side data, no handshake */
58 * VIA pin | Egret pin
59 * ----------------+------------------------------------------
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
143 CS_MRST_CLR = 1<<3, /* Clear Master reset */
144 CS_MRST_SET = 1<<2, /* Set Master reset */
145 CS_RST_CLR = 1<<1, /* Clear Software reset */
146 CS_RST_SET = 1, /* Set Software reset */
217 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
223 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/sunxi/
H A Dsunxi_display.c4 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
5 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
7 * SPDX-License-Identifier: GPL-2.0+
73 * Wait up to 200ms for value to be set in given part of reg.
82 return -ETIME; in await_completion()
100 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, in sunxi_hdmi_hpd_detect()
105 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
107 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
110 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()
112 writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl); in sunxi_hdmi_hpd_detect()
[all …]
/OK3568_Linux_fs/u-boot/board/gateworks/gw_ventana/
H A Dgw_ventana.c6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/mx6-pins.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/sata.h>
19 #include <asm/mach-imx/spi.h>
20 #include <asm/mach-imx/video.h>
107 clrsetbits_le32(&mxc_ccm->cs2cdr, in setup_gpmi_nand()
116 setbits_le32(&mxc_ccm->CCGR4, in setup_gpmi_nand()
124 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); in setup_gpmi_nand()
154 /* Reset USB HUB */ in board_ehci_hcd_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/octeon-usb/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
172 * This value is in terms of 32-bit words.
181 * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType)
[all …]
/OK3568_Linux_fs/kernel/drivers/iio/light/
H A Drpr0521.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RPR-0521 ROHM Ambient Light and Proximity Sensor
7 * IIO driver for RPR-0521RS (7-bit I2C slave address 0x38).
31 #define RPR0521_REG_PXS_DATA 0x44 /* 16-bit, little endian */
32 #define RPR0521_REG_ALS_DATA0 0x46 /* 16-bit, little endian */
33 #define RPR0521_REG_ALS_DATA1 0x48 /* 16-bit, little endian */
68 #define RPR0521_DEFAULT_MEAS_TIME 0x06 /* ALS - 100ms, PXS - 100ms */
170 {2, 500000, 20, 0}, /* 1000, measurement 100ms, sleep 300ms */
171 {2, 500000, 10, 0}, /* 1001, measurement 100ms, sleep 300ms */
190 /* optimize runtime pm ops - enable/disable device only if needed */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/
H A Dsiutils.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Misc utility routines for accessing chip-specific features
4 * of the SiliconBackplane-based Broadcom chips.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: siutils.c 668442 2016-11-03 08:42:43Z $
81 * the write. During that time the 'SlowWritePending' bit in the PMUStatus register is set.
139 * devid - pci device id (used to determine chip#)
140 * osh - opaque OS handle
141 * regs - virtual address of initial core registers
[all …]
/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
36 /*-----------------------------------------------------------*/
114 for (; timeout > 0; timeout--) { in comphy_poll_reg()
126 debug("Time out waiting (%p = %#010x)\n", addr, rval); in comphy_poll_reg()
213 * 11. Release SW reset in comphy_pcie_power_up()
222 /* Assert PCLK enabled */ in comphy_pcie_power_up()
256 * 1. Select 40-bit data width width in comphy_sata_power_up()
281 * 4. Reset reserved bit (??) in comphy_sata_power_up()
287 * 5. Set vendor-specific configuration (??) in comphy_sata_power_up()
[all …]
/OK3568_Linux_fs/kernel/drivers/bluetooth/
H A Dhci_bcm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
52 * struct bcm_device_data - device specific data
61 * struct bcm_device - device driver resources
66 * @device_wakeup: BT_WAKE pin,
67 * assert = Bluetooth device must wake up or remain awake,
69 * @shutdown: BT_REG_ON pin,
71 * @set_device_wakeup: callback to toggle BT_WAKE pin
73 * @set_shutdown: callback to toggle BT_REG_ON pin
75 * @btlp: Apple ACPI method to toggle BT_WAKE pin ("Bluetooth Low Power")
76 * @btpu: Apple ACPI method to drive BT_REG_ON pin high ("Bluetooth Power Up")
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
69 unsigned int delay = dev->d3hot_delay; in pci_dev_d3_sleep()
70 int err = -EOPNOTSUPP; in pci_dev_d3_sleep()
77 if (err == -EOPNOTSUPP) in pci_dev_d3_sleep()
98 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
109 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
126 * measured in 32-bit words, not bytes.
[all …]

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