Home
last modified time | relevance | path

Searched +full:reset +full:- +full:assert +full:- +full:us (Results 1 – 25 of 583) sorted by relevance

12345678910>>...24

/OK3568_Linux_fs/kernel/drivers/reset/
H A Dreset-imx7.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * i.MX7 System Reset Controller (SRC) driver
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/reset/imx7-reset.h>
17 #include <dt-bindings/reset/imx8mq-reset.h>
18 #include <dt-bindings/reset/imx8mp-reset.h>
51 const struct imx7_src_signal *signal = &imx7src->signals[id]; in imx7_reset_update()
53 return regmap_update_bits(imx7src->regmap, in imx7_reset_update()
54 signal->offset, signal->bit, value); in imx7_reset_update()
92 unsigned long id, bool assert) in imx7_reset_set() argument
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c2 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
23 writel(val, &clock_manager_base->bypass); in cm_write_bypass()
30 writel(val, &clock_manager_base->ctrl); in cm_write_ctrl()
54 * Put all plls VCO registers back to reset value (bandgap power down).
55 * Put peripheral and main pll src to reset value to avoid glitch.
56 * Delay 5 us.
58 * Start 7 us timer.
60 * Wait for 7 us timer.
64 * Assert/deassert outreset all.
[all …]
H A Dfreeze_controller.c4 * SPDX-License-Identifier: GPL-2.0+
20 * Default state from cold reset is FREEZE_ALL; the global
36 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); in sys_mgr_frzctrl_freeze_req()
41 &freeze_controller_base->vioctrl + channel_id); in sys_mgr_frzctrl_freeze_req()
44 * Assert active low enrnsl, plniotri in sys_mgr_frzctrl_freeze_req()
55 * Assert active low bhniotri signal and de-assert in sys_mgr_frzctrl_freeze_req()
69 * Assert active low enrnsl, plniotri and in sys_mgr_frzctrl_freeze_req()
76 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
79 * assert active low bhniotri & nfrzdrv signals, in sys_mgr_frzctrl_freeze_req()
80 * de-assert active high csrdone and assert in sys_mgr_frzctrl_freeze_req()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
24 "#address-cells":
27 "#size-cells":
30 reset-gpios:
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt4 or interrupt-based thermal monitoring, CPU and GPU throttling based
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
18 - soctherm-reg
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-kii-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb-p20x.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
14 compatible = "videostrong,kii-pro", "amlogic,meson-gxbb";
18 compatible = "gpio-leds";
21 default-state = "off";
27 gpio-keys-polled {
[all …]
H A Dmeson-gxm-q200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
11 #include "meson-gxm.dtsi"
12 #include "meson-gx-p23x-q20x.dtsi"
15 compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
[all …]
H A Dmeson-gxl-s905d-p230.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/input/input.h>
11 #include "meson-gxl-s905d.dtsi"
12 #include "meson-gx-p23x-q20x.dtsi"
15 compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
18 adc-keys {
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
[all …]
H A Dmeson-gxbb-p200.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb-p20x.dtsi"
11 #include <dt-bindings/input/input.h>
14 compatible = "amlogic,p200", "amlogic,meson-gxbb";
17 avdd18_usb_adc: regulator-avdd18_usb_adc {
18 compatible = "regulator-fixed";
19 regulator-name = "AVDD18_USB_ADC";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
[all …]
H A Dmeson-gxm-nexbox-a1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "meson-gxm.dtsi"
15 compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm";
24 stdout-path = "serial0:115200n8";
32 vddio_boot: regulator-vddio-boot {
33 compatible = "regulator-fixed";
34 regulator-name = "VDDIO_BOOT";
35 regulator-min-microvolt = <1800000>;
36 regulator-max-microvolt = <1800000>;
[all …]
H A Dmeson-gxm-rbox-pro.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Andreas Färber
5 * Based on nexbox-a1:
14 /dts-v1/;
16 #include "meson-gxm.dtsi"
19 compatible = "kingnovel,r-box-pro", "amlogic,s912", "amlogic,meson-gxm";
20 model = "R-Box Pro";
28 stdout-path = "serial0:115200n8";
37 compatible = "gpio-leds";
39 led-blue {
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.i2c4 While I2C supports multi-master buses this is difficult to get right.
6 Clock-stretching and the arbitrary time that an I2C transaction can take
8 When one or more masters can be reset independently part-way through a
11 U-Boot provides a scheme based on two 'claim' GPIOs, one driven by the
18 Since U-Boot runs on the AP, the terminology used is 'our' claim GPIO,
23 i2c-arb-gpio-challenge for the implementation.
28 - AP_CLAIM: output from AP, signalling to the EC that the AP wants the bus
29 - EC_CLAIM: output from EC, signalling to the AP that the EC wants the bus
31 The basic algorithm is to assert your line when you want the bus, then make
50 To release the bus, just de-assert the claim line.
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
46 * H/W requires a 5us delay between disabling the bypass and in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
[all …]
H A Dclk-hfpll.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
13 #include "clk-hfpll.h"
23 struct hfpll_data const *hd = h->d; in __clk_hfpll_init_once()
24 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_init_once()
26 if (likely(h->init_done)) in __clk_hfpll_init_once()
30 if (hd->config_val) in __clk_hfpll_init_once()
31 regmap_write(regmap, hd->config_reg, hd->config_val); in __clk_hfpll_init_once()
32 regmap_write(regmap, hd->m_reg, 0); in __clk_hfpll_init_once()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dstm32mp157c-odyssey.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp157c-odyssey-som.dtsi"
11 model = "Seeed Studio Odyssey-STM32MP157C Board";
12 compatible = "seeed,stm32mp157c-odyssey",
13 "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
21 stdout-path = "serial0:115200n8";
27 pinctrl-0 = <&ethernet0_rgmii_pins_a>;
28 pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
29 pinctrl-names = "default", "sleep";
[all …]
H A Dmeson8b-mxq.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
22 stdout-path = "serial0:115200n8";
30 iio-hwmon {
31 compatible = "iio-hwmon";
32 io-channels = <&saradc 8>;
35 vcck: regulator-vcck {
36 compatible = "pwm-regulator";
38 regulator-name = "VCCK";
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/fieldbus/anybuss/
H A Darcx-anybus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arcx Anybus-S Controller driver
23 /* move to <linux/anybuss-controller.h> when taking this out of staging */
24 #include "anybuss-controller.h"
50 static void do_reset(struct controller_priv *cd, u8 rst_bit, bool reset) in do_reset() argument
52 mutex_lock(&cd->ctrl_lock); in do_reset()
54 * CPLD_CONTROL is write-only, so cache its value in in do_reset()
55 * cd->control_reg in do_reset()
57 if (reset) in do_reset()
58 cd->control_reg &= ~rst_bit; in do_reset()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_pll_8960.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
27 * configuration into common-clock-framework.
239 msm_writel(data, pll->mmio + reg); in pll_write()
244 return msm_readl(pll->mmio + reg); in pll_read()
249 return platform_get_drvdata(pll->pdev); in pll_get_phy()
261 /* Assert PLL S/W reset */ in hdmi_pll_enable()
266 /* Wait for a short time before de-asserting in hdmi_pll_enable()
269 * to assert and de-assert. in hdmi_pll_enable()
273 /* De-assert PLL S/W reset */ in hdmi_pll_enable()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/infineon/
H A Dpcie_core.c8 * Copyright (C) 1999-2017, Broadcom Corporation
29 * <<Broadcom-WL-IPTag/Open:>>
31 * $Id: pcie_core.c 701962 2017-05-30 06:13:15Z $
73 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
74 if (CCREV(sih->ccrev) < 65) { in pcie_watchdog_reset()
80 if (CCREV(sih->ccrev) < 67) { in pcie_watchdog_reset()
81 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
90 ASSERT(pcieregs != NULL); in pcie_watchdog_reset()
92 /* Disable/restore ASPM Control to protect the watchdog reset */ in pcie_watchdog_reset()
93 W_REG(osh, &pcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL); in pcie_watchdog_reset()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/
H A Dpcie_core.c8 * Copyright (C) 1999-2017, Broadcom Corporation
29 * <<Broadcom-WL-IPTag/Open:>>
31 * $Id: pcie_core.c 701962 2017-05-30 06:13:15Z $
73 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
74 if (CCREV(sih->ccrev) < 65) { in pcie_watchdog_reset()
80 if (CCREV(sih->ccrev) < 67) { in pcie_watchdog_reset()
81 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
90 ASSERT(pcieregs != NULL); in pcie_watchdog_reset()
92 /* Disable/restore ASPM Control to protect the watchdog reset */ in pcie_watchdog_reset()
93 W_REG(osh, &pcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL); in pcie_watchdog_reset()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/
H A Dpcie_core.c8 * Copyright (C) 1999-2017, Broadcom Corporation
29 * <<Broadcom-WL-IPTag/Open:>>
31 * $Id: pcie_core.c 701962 2017-05-30 06:13:15Z $
73 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
74 if (CCREV(sih->ccrev) < 65) { in pcie_watchdog_reset()
80 if (CCREV(sih->ccrev) < 67) { in pcie_watchdog_reset()
81 /* To avoid hang on FPGA, donot reset watchdog */ in pcie_watchdog_reset()
90 ASSERT(pcieregs != NULL); in pcie_watchdog_reset()
92 /* Disable/restore ASPM Control to protect the watchdog reset */ in pcie_watchdog_reset()
93 W_REG(osh, &pcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL); in pcie_watchdog_reset()
[all …]
/OK3568_Linux_fs/u-boot/board/kosagi/novena/
H A Dnovena_spl.c6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h>
17 #include <asm/mach-imx/boot_mode.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h>
26 #include <asm/arch/mx6-ddr.h>
131 /* Assert Ethernet PHY nRST */ in novena_spl_setup_iomux_enet()
135 * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset in novena_spl_setup_iomux_enet()
136 * de-assertion. The intention is to use weak signal drivers (pull-ups) in novena_spl_setup_iomux_enet()
[all …]
/OK3568_Linux_fs/kernel/drivers/fpga/
H A Dice40-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/fpga/fpga-mgr.h>
21 #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */
22 #define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */
28 struct gpio_desc *reset; member
34 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_state()
36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : in ice40_fpga_ops_state()
44 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_write_init()
45 struct spi_device *dev = priv->dev; in ice40_fpga_ops_write_init()
62 if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { in ice40_fpga_ops_write_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/remoteproc/
H A Dqcom_q6v5_wcss.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Linaro Ltd.
5 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
14 #include <linux/reset.h>
106 /* Assert resets, stop core */ in q6v5_wcss_reset()
107 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
109 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
112 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
114 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
117 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
[all …]

12345678910>>...24