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/OK3568_Linux_fs/kernel/drivers/staging/sm750fb/
H A Dddk750_power.c1 // SPDX-License-Identifier: GPL-2.0
30 * On hardware reset, power mode 0 is default.
58 /* Set up other fields in Power Control Register */ in sm750_set_power_mode()
71 /* Program new power mode. */ in sm750_set_power_mode()
75 void sm750_set_current_gate(unsigned int gate) in sm750_set_current_gate() argument
78 poke32(MODE1_GATE, gate); in sm750_set_current_gate()
80 poke32(MODE0_GATE, gate); in sm750_set_current_gate()
88 u32 gate; in sm750_enable_2d_engine() local
90 gate = peek32(CURRENT_GATE); in sm750_enable_2d_engine()
92 gate |= (CURRENT_GATE_DE | CURRENT_GATE_CSC); in sm750_enable_2d_engine()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Ddra7xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,dra7-atl-clock";
18 #clock-cells = <0>;
19 compatible = "ti,dra7-atl-clock";
24 #clock-cells = <0>;
25 compatible = "ti,dra7-atl-clock";
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
[all …]
H A Domap34xx-omap36xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "fixed-factor-clock";
15 clock-mult = <1>;
16 clock-div = <1>;
20 #clock-cells = <0>;
21 compatible = "ti,omap3-interface-clock";
23 ti,bit-shift = <3>;
28 #clock-cells = <0>;
29 compatible = "ti,omap3-interface-clock";
32 ti,bit-shift = <2>;
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H A Dam33xx-clocks.dtsi12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
15 ti,bit-shift = <22>;
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
23 clock-mult = <1>;
24 clock-div = <1>;
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
31 clock-mult = <1>;
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/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos4412-isp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/clock/exynos4.h>
12 #include <linux/clk-provider.h>
19 /* Exynos4x12 specific registers, which belong to ISP power domain */
48 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
49 GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
50 GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
51 GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
52 GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
53 GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/mxs/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
14 * struct clk_pll - mxs pll clock
17 * @power: the shift of power bit
20 * The mxs pll is a fixed rate clock with power and gate control,
21 * and the shift of gate bit is always 31.
26 u8 power; member
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
47 writel_relaxed(1 << pll->power, pll->base + CLR); in clk_pll_unprepare()
54 writel_relaxed(1 << 31, pll->base + CLR); in clk_pll_enable()
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/OK3568_Linux_fs/kernel/drivers/media/tuners/
H A Dfc0013.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
11 #include "fc0013-priv.h"
17 .addr = priv->addr, .flags = 0, .buf = buf, .len = 2 in fc0013_writereg()
20 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0013_writereg()
22 return -EREMOTEIO; in fc0013_writereg()
30 { .addr = priv->addr, .flags = 0, .buf = &reg, .len = 1 }, in fc0013_readreg()
31 { .addr = priv->addr, .flags = I2C_M_RD, .buf = val, .len = 1 }, in fc0013_readreg()
34 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in fc0013_readreg()
36 return -EREMOTEIO; in fc0013_readreg()
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H A Dfc0012.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
9 #include "fc0012-priv.h"
15 .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 in fc0012_writereg()
18 if (i2c_transfer(priv->i2c, &msg, 1) != 1) { in fc0012_writereg()
19 dev_err(&priv->i2c->dev, in fc0012_writereg()
22 return -EREMOTEIO; in fc0012_writereg()
30 { .addr = priv->cfg->i2c_address, .flags = 0, in fc0012_readreg()
32 { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, in fc0012_readreg()
36 if (i2c_transfer(priv->i2c, msg, 2) != 2) { in fc0012_readreg()
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/OK3568_Linux_fs/kernel/arch/arm/mach-mmp/
H A Dpm-mmp2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MMP2 Power Management Routines
18 #include <asm/mach-types.h>
21 #include "addr-map.h"
22 #include "pm-mmp2.h"
23 #include "regs-icu.h"
29 int irq = d->irq; in mmp2_set_wake()
63 /* close AXI fabric clock gate */ in pm_scu_clk_disable()
67 /* close MCB master clock gate */ in pm_scu_clk_disable()
79 /* open AXI fabric clock gate */ in pm_scu_clk_enable()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/hibmc/
H A Dhibmc_drm_de.c1 // SPDX-License-Identifier: GPL-2.0-or-later
55 #define PADDING(align, data) (((data) + (align) - 1) & (~((align) - 1)))
60 struct drm_framebuffer *fb = state->fb; in hibmc_plane_atomic_check()
61 struct drm_crtc *crtc = state->crtc; in hibmc_plane_atomic_check()
63 u32 src_w = state->src_w >> 16; in hibmc_plane_atomic_check()
64 u32 src_h = state->src_h >> 16; in hibmc_plane_atomic_check()
69 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); in hibmc_plane_atomic_check()
73 if (src_w != state->crtc_w || src_h != state->crtc_h) { in hibmc_plane_atomic_check()
74 drm_dbg_atomic(plane->dev, "scale not support\n"); in hibmc_plane_atomic_check()
75 return -EINVAL; in hibmc_plane_atomic_check()
[all …]
H A Dhibmc_drm_drv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 (struct hibmc_drm_private *)dev->dev_private; in hibmc_drm_interrupt()
36 status = readl(priv->mmio + HIBMC_RAW_INTERRUPT); in hibmc_drm_interrupt()
40 priv->mmio + HIBMC_RAW_INTERRUPT); in hibmc_drm_interrupt()
85 drm_mode_config_init(priv->dev); in hibmc_kms_init()
86 priv->mode_config_initialized = true; in hibmc_kms_init()
88 priv->dev->mode_config.min_width = 0; in hibmc_kms_init()
89 priv->dev->mode_config.min_height = 0; in hibmc_kms_init()
90 priv->dev->mode_config.max_width = 1920; in hibmc_kms_init()
91 priv->dev->mode_config.max_height = 1200; in hibmc_kms_init()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
15 is used to locally gate the clocks for the associated peripheral.
24 include/dt-bindings/clock/imx8-clock.h
29 - fsl,imx8qxp-lpcg-adma
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/OK3568_Linux_fs/kernel/drivers/clk/pxa/
H A Dclk-pxa.h1 /* SPDX-License-Identifier: GPL-2.0-only */
92 * - a low power parent
93 * - a normal parent
95 * +------------+ +-----------+
96 * | Low Power | --- | x mult_lp |
98 * +------------+ +-----------+ \+-----+ +-----------+
99 * | Mux |---| CKEN gate |
100 * +------------+ +-----------+ /+-----+ +-----------+
101 * | High Power | | x mult_hp |/
102 * | Clock | --- | / div_hp |
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/OK3568_Linux_fs/kernel/Documentation/trace/coresight/
H A Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
35 channel gate.
42 attached CTIs will also be enabled. By default/on power up the CTIs have
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Domap34xx-omap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
17 #clock-cells = <0>;
18 compatible = "ti,omap3-interface-clock";
20 ti,bit-shift = <3>;
25 #clock-cells = <0>;
26 compatible = "ti,omap3-interface-clock";
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H A Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-tegra/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
80 * The power up sequence of cold boot CPU and warm boot CPU in tegra30_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
103 * The power status of the cold boot CPU is power gated as in tegra30_boot_secondary()
104 * default. To power up the cold boot CPU, the power should in tegra30_boot_secondary()
105 * be un-gated by un-toggling the power gate register in tegra30_boot_secondary()
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/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dhi6220-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
41 /* gate clocks */
60 /* gate clock */
124 /* gate clock */
130 /* gate clocks */
161 /* clk in Hi6220 power controller */
162 /* gate clocks */
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/gyroscope/
H A Dinvensense,mpu3050.txt1 Invensense MPU-3050 Gyroscope device tree bindings
4 - compatible : should be "invensense,mpu3050"
5 - reg : the I2C address of the sensor
8 - interrupts : interrupt mapping for the trigger interrupt from the
13 - vdd-supply : supply regulator for the main power voltage.
14 - vlogic-supply : supply regulator for the signal voltage.
15 - mount-matrix : see iio/mount-matrix.txt
18 - The MPU-3050 will pass through and forward the I2C signals from the
21 i2c gate node. For details see: i2c/i2c-gate.txt
28 interrupt-parent = <&foo>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dhisilicon-histb-pcie.txt6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxm-khadas-vim2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
12 #include "meson-gxm.dtsi"
15 compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
24 stdout-path = "serial0:115200n8";
32 adc-keys {
33 compatible = "adc-keys";
34 io-channels = <&saradc 0>;
35 io-channel-names = "buttons";
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/ingenic/
H A Djz4770-cgu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/jz4770-cgu.h>
47 #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
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