1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Aisheng Dong <aisheng.dong@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The Low-Power Clock Gate (LPCG) modules contain a local programming 14*4882a593Smuzhiyun model to control the clock gates for the peripherals. An LPCG module 15*4882a593Smuzhiyun is used to locally gate the clocks for the associated peripheral. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun This level of clock gating is provided after the clocks are generated 18*4882a593Smuzhiyun by the SCU resources and clock controls. Thus even if the clock is 19*4882a593Smuzhiyun enabled by these control bits, it might still not be running based 20*4882a593Smuzhiyun on the base resource. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun The clock consumer should specify the desired clock by having the clock 23*4882a593Smuzhiyun ID in its "clocks" phandle cell. See the full list of clock IDs from: 24*4882a593Smuzhiyun include/dt-bindings/clock/imx8-clock.h 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunproperties: 27*4882a593Smuzhiyun compatible: 28*4882a593Smuzhiyun enum: 29*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-adma 30*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-conn 31*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-dc 32*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-dsp 33*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-gpu 34*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-hsio 35*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-img 36*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-lsio 37*4882a593Smuzhiyun - fsl,imx8qxp-lpcg-vpu 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun reg: 40*4882a593Smuzhiyun maxItems: 1 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun '#clock-cells': 43*4882a593Smuzhiyun const: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyunrequired: 46*4882a593Smuzhiyun - compatible 47*4882a593Smuzhiyun - reg 48*4882a593Smuzhiyun - '#clock-cells' 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunadditionalProperties: false 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunexamples: 53*4882a593Smuzhiyun - | 54*4882a593Smuzhiyun #include <dt-bindings/clock/imx8-clock.h> 55*4882a593Smuzhiyun #include <dt-bindings/firmware/imx/rsrc.h> 56*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun clock-controller@5b200000 { 59*4882a593Smuzhiyun compatible = "fsl,imx8qxp-lpcg-conn"; 60*4882a593Smuzhiyun reg = <0x5b200000 0xb0000>; 61*4882a593Smuzhiyun #clock-cells = <1>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun mmc@5b010000 { 65*4882a593Smuzhiyun compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 66*4882a593Smuzhiyun interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 67*4882a593Smuzhiyun reg = <0x5b010000 0x10000>; 68*4882a593Smuzhiyun clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 69*4882a593Smuzhiyun <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 70*4882a593Smuzhiyun <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 71*4882a593Smuzhiyun clock-names = "ipg", "per", "ahb"; 72*4882a593Smuzhiyun power-domains = <&pd IMX_SC_R_SDHC_0>; 73*4882a593Smuzhiyun }; 74