1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015 Hisilicon Limited. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Bintian Wang <bintian.wang@huawei.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_HI6220_H 9*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_HI6220_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* clk in Hi6220 AO (always on) controller */ 12*4882a593Smuzhiyun #define HI6220_NONE_CLOCK 0 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* fixed rate clocks */ 15*4882a593Smuzhiyun #define HI6220_REF32K 1 16*4882a593Smuzhiyun #define HI6220_CLK_TCXO 2 17*4882a593Smuzhiyun #define HI6220_MMC1_PAD 3 18*4882a593Smuzhiyun #define HI6220_MMC2_PAD 4 19*4882a593Smuzhiyun #define HI6220_MMC0_PAD 5 20*4882a593Smuzhiyun #define HI6220_PLL_BBP 6 21*4882a593Smuzhiyun #define HI6220_PLL_GPU 7 22*4882a593Smuzhiyun #define HI6220_PLL1_DDR 8 23*4882a593Smuzhiyun #define HI6220_PLL_SYS 9 24*4882a593Smuzhiyun #define HI6220_PLL_SYS_MEDIA 10 25*4882a593Smuzhiyun #define HI6220_DDR_SRC 11 26*4882a593Smuzhiyun #define HI6220_PLL_MEDIA 12 27*4882a593Smuzhiyun #define HI6220_PLL_DDR 13 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* fixed factor clocks */ 30*4882a593Smuzhiyun #define HI6220_300M 14 31*4882a593Smuzhiyun #define HI6220_150M 15 32*4882a593Smuzhiyun #define HI6220_PICOPHY_SRC 16 33*4882a593Smuzhiyun #define HI6220_MMC0_SRC_SEL 17 34*4882a593Smuzhiyun #define HI6220_MMC1_SRC_SEL 18 35*4882a593Smuzhiyun #define HI6220_MMC2_SRC_SEL 19 36*4882a593Smuzhiyun #define HI6220_VPU_CODEC 20 37*4882a593Smuzhiyun #define HI6220_MMC0_SMP 21 38*4882a593Smuzhiyun #define HI6220_MMC1_SMP 22 39*4882a593Smuzhiyun #define HI6220_MMC2_SMP 23 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* gate clocks */ 42*4882a593Smuzhiyun #define HI6220_WDT0_PCLK 24 43*4882a593Smuzhiyun #define HI6220_WDT1_PCLK 25 44*4882a593Smuzhiyun #define HI6220_WDT2_PCLK 26 45*4882a593Smuzhiyun #define HI6220_TIMER0_PCLK 27 46*4882a593Smuzhiyun #define HI6220_TIMER1_PCLK 28 47*4882a593Smuzhiyun #define HI6220_TIMER2_PCLK 29 48*4882a593Smuzhiyun #define HI6220_TIMER3_PCLK 30 49*4882a593Smuzhiyun #define HI6220_TIMER4_PCLK 31 50*4882a593Smuzhiyun #define HI6220_TIMER5_PCLK 32 51*4882a593Smuzhiyun #define HI6220_TIMER6_PCLK 33 52*4882a593Smuzhiyun #define HI6220_TIMER7_PCLK 34 53*4882a593Smuzhiyun #define HI6220_TIMER8_PCLK 35 54*4882a593Smuzhiyun #define HI6220_UART0_PCLK 36 55*4882a593Smuzhiyun #define HI6220_RTC0_PCLK 37 56*4882a593Smuzhiyun #define HI6220_RTC1_PCLK 38 57*4882a593Smuzhiyun #define HI6220_AO_NR_CLKS 39 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* clk in Hi6220 systrl */ 60*4882a593Smuzhiyun /* gate clock */ 61*4882a593Smuzhiyun #define HI6220_MMC0_CLK 1 62*4882a593Smuzhiyun #define HI6220_MMC0_CIUCLK 2 63*4882a593Smuzhiyun #define HI6220_MMC1_CLK 3 64*4882a593Smuzhiyun #define HI6220_MMC1_CIUCLK 4 65*4882a593Smuzhiyun #define HI6220_MMC2_CLK 5 66*4882a593Smuzhiyun #define HI6220_MMC2_CIUCLK 6 67*4882a593Smuzhiyun #define HI6220_USBOTG_HCLK 7 68*4882a593Smuzhiyun #define HI6220_CLK_PICOPHY 8 69*4882a593Smuzhiyun #define HI6220_HIFI 9 70*4882a593Smuzhiyun #define HI6220_DACODEC_PCLK 10 71*4882a593Smuzhiyun #define HI6220_EDMAC_ACLK 11 72*4882a593Smuzhiyun #define HI6220_CS_ATB 12 73*4882a593Smuzhiyun #define HI6220_I2C0_CLK 13 74*4882a593Smuzhiyun #define HI6220_I2C1_CLK 14 75*4882a593Smuzhiyun #define HI6220_I2C2_CLK 15 76*4882a593Smuzhiyun #define HI6220_I2C3_CLK 16 77*4882a593Smuzhiyun #define HI6220_UART1_PCLK 17 78*4882a593Smuzhiyun #define HI6220_UART2_PCLK 18 79*4882a593Smuzhiyun #define HI6220_UART3_PCLK 19 80*4882a593Smuzhiyun #define HI6220_UART4_PCLK 20 81*4882a593Smuzhiyun #define HI6220_SPI_CLK 21 82*4882a593Smuzhiyun #define HI6220_TSENSOR_CLK 22 83*4882a593Smuzhiyun #define HI6220_MMU_CLK 23 84*4882a593Smuzhiyun #define HI6220_HIFI_SEL 24 85*4882a593Smuzhiyun #define HI6220_MMC0_SYSPLL 25 86*4882a593Smuzhiyun #define HI6220_MMC1_SYSPLL 26 87*4882a593Smuzhiyun #define HI6220_MMC2_SYSPLL 27 88*4882a593Smuzhiyun #define HI6220_MMC0_SEL 28 89*4882a593Smuzhiyun #define HI6220_MMC1_SEL 29 90*4882a593Smuzhiyun #define HI6220_BBPPLL_SEL 30 91*4882a593Smuzhiyun #define HI6220_MEDIA_PLL_SRC 31 92*4882a593Smuzhiyun #define HI6220_MMC2_SEL 32 93*4882a593Smuzhiyun #define HI6220_CS_ATB_SYSPLL 33 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* mux clocks */ 96*4882a593Smuzhiyun #define HI6220_MMC0_SRC 34 97*4882a593Smuzhiyun #define HI6220_MMC0_SMP_IN 35 98*4882a593Smuzhiyun #define HI6220_MMC1_SRC 36 99*4882a593Smuzhiyun #define HI6220_MMC1_SMP_IN 37 100*4882a593Smuzhiyun #define HI6220_MMC2_SRC 38 101*4882a593Smuzhiyun #define HI6220_MMC2_SMP_IN 39 102*4882a593Smuzhiyun #define HI6220_HIFI_SRC 40 103*4882a593Smuzhiyun #define HI6220_UART1_SRC 41 104*4882a593Smuzhiyun #define HI6220_UART2_SRC 42 105*4882a593Smuzhiyun #define HI6220_UART3_SRC 43 106*4882a593Smuzhiyun #define HI6220_UART4_SRC 44 107*4882a593Smuzhiyun #define HI6220_MMC0_MUX0 45 108*4882a593Smuzhiyun #define HI6220_MMC1_MUX0 46 109*4882a593Smuzhiyun #define HI6220_MMC2_MUX0 47 110*4882a593Smuzhiyun #define HI6220_MMC0_MUX1 48 111*4882a593Smuzhiyun #define HI6220_MMC1_MUX1 49 112*4882a593Smuzhiyun #define HI6220_MMC2_MUX1 50 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* divider clocks */ 115*4882a593Smuzhiyun #define HI6220_CLK_BUS 51 116*4882a593Smuzhiyun #define HI6220_MMC0_DIV 52 117*4882a593Smuzhiyun #define HI6220_MMC1_DIV 53 118*4882a593Smuzhiyun #define HI6220_MMC2_DIV 54 119*4882a593Smuzhiyun #define HI6220_HIFI_DIV 55 120*4882a593Smuzhiyun #define HI6220_BBPPLL0_DIV 56 121*4882a593Smuzhiyun #define HI6220_CS_DAPB 57 122*4882a593Smuzhiyun #define HI6220_CS_ATB_DIV 58 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* gate clock */ 125*4882a593Smuzhiyun #define HI6220_DAPB_CLK 59 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define HI6220_SYS_NR_CLKS 60 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* clk in Hi6220 media controller */ 130*4882a593Smuzhiyun /* gate clocks */ 131*4882a593Smuzhiyun #define HI6220_DSI_PCLK 1 132*4882a593Smuzhiyun #define HI6220_G3D_PCLK 2 133*4882a593Smuzhiyun #define HI6220_ACLK_CODEC_VPU 3 134*4882a593Smuzhiyun #define HI6220_ISP_SCLK 4 135*4882a593Smuzhiyun #define HI6220_ADE_CORE 5 136*4882a593Smuzhiyun #define HI6220_MED_MMU 6 137*4882a593Smuzhiyun #define HI6220_CFG_CSI4PHY 7 138*4882a593Smuzhiyun #define HI6220_CFG_CSI2PHY 8 139*4882a593Smuzhiyun #define HI6220_ISP_SCLK_GATE 9 140*4882a593Smuzhiyun #define HI6220_ISP_SCLK_GATE1 10 141*4882a593Smuzhiyun #define HI6220_ADE_CORE_GATE 11 142*4882a593Smuzhiyun #define HI6220_CODEC_VPU_GATE 12 143*4882a593Smuzhiyun #define HI6220_MED_SYSPLL 13 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* mux clocks */ 146*4882a593Smuzhiyun #define HI6220_1440_1200 14 147*4882a593Smuzhiyun #define HI6220_1000_1200 15 148*4882a593Smuzhiyun #define HI6220_1000_1440 16 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* divider clocks */ 151*4882a593Smuzhiyun #define HI6220_CODEC_JPEG 17 152*4882a593Smuzhiyun #define HI6220_ISP_SCLK_SRC 18 153*4882a593Smuzhiyun #define HI6220_ISP_SCLK1 19 154*4882a593Smuzhiyun #define HI6220_ADE_CORE_SRC 20 155*4882a593Smuzhiyun #define HI6220_ADE_PIX_SRC 21 156*4882a593Smuzhiyun #define HI6220_G3D_CLK 22 157*4882a593Smuzhiyun #define HI6220_CODEC_VPU_SRC 23 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define HI6220_MEDIA_NR_CLKS 24 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* clk in Hi6220 power controller */ 162*4882a593Smuzhiyun /* gate clocks */ 163*4882a593Smuzhiyun #define HI6220_PLL_GPU_GATE 1 164*4882a593Smuzhiyun #define HI6220_PLL1_DDR_GATE 2 165*4882a593Smuzhiyun #define HI6220_PLL_DDR_GATE 3 166*4882a593Smuzhiyun #define HI6220_PLL_MEDIA_GATE 4 167*4882a593Smuzhiyun #define HI6220_PLL0_BBP_GATE 5 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* divider clocks */ 170*4882a593Smuzhiyun #define HI6220_DDRC_SRC 6 171*4882a593Smuzhiyun #define HI6220_DDRC_AXI1 7 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define HI6220_POWER_NR_CLKS 8 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* clk in Hi6220 acpu sctrl */ 176*4882a593Smuzhiyun #define HI6220_ACPU_SFT_AT_S 0 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #endif 179