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/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument
35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees()
36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees()
37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees()
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local
47 regval = readl(phase->reg); in hisi_clk_get_phase()
48 regval = (regval & phase->mask) >> phase->shift; in hisi_clk_get_phase()
50 return hisi_phase_regval_to_degrees(phase, regval); in hisi_clk_get_phase()
53 static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, in hisi_phase_degrees_to_regval() argument
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_read_leveling.c56 * Desc: Execute the Read leveling phase by HW
92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
109 phase = (reg >> REG_PHY_PHASE_OFFS) & in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
113 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
114 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
115 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
116 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
139 DEBUG_RL_S(", Phase: "); in ddr3_read_leveling_hw()
174 * Desc: Execute the Read leveling phase by SW
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H A Dddr3_write_leveling.c59 * Desc: Execute Write leveling phase by HW
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
118 phase = in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
134 /* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */ in ddr3_write_leveling_hw()
146 DEBUG_WL_S(", Phase: "); in ddr3_write_leveling_hw()
187 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
344 phase = in ddr3_wl_supplement()
352 [P] = phase; in ddr3_wl_supplement()
362 phase, delay); in ddr3_wl_supplement()
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/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
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/OK3568_Linux_fs/kernel/Documentation/hwmon/
H A Dmax16601.rst64 curr2_input VCORE phase 0 input current.
67 curr3_input VCORE phase 1 input current.
70 curr4_input VCORE phase 2 input current.
73 curr5_input VCORE phase 3 input current.
76 curr6_input VCORE phase 4 input current.
79 curr7_input VCORE phase 5 input current.
82 curr8_input VCORE phase 6 input current.
85 curr9_input VCORE phase 7 input current.
101 curr13_input VCORE phase 0 output current.
104 curr14_input VCORE phase 1 output current.
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
83 SRII(PHASE, DP_DTO, 2),\
84 SRII(PHASE, DP_DTO, 3),\
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/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A Dclk-mod0.c175 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
181 value = readl(phase->reg); in mmc_get_phase()
182 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
217 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
268 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
269 value = readl(phase->reg); in mmc_set_phase()
270 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
271 value |= delay << phase->offset; in mmc_set_phase()
272 writel(value, phase->reg); in mmc_set_phase()
273 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
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/OK3568_Linux_fs/kernel/drivers/hwmon/pmbus/
H A Dmp2975.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
90 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, in mp2975_read_word_helper() argument
93 int ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_word_helper()
122 int page, int phase, u8 reg) in mp2975_read_phase() argument
126 ret = pmbus_read_word_data(client, page, phase, reg); in mp2975_read_phase()
130 if (!((phase + 1) % MP2975_PAGE_NUM)) in mp2975_read_phase()
141 * - Rcs is the internal phase current sense resistor which is constant in mp2975_read_phase()
147 * Current phase sensing, providing by the device is not accurate in mp2975_read_phase()
150 * case phase current is represented as the maximum between the value in mp2975_read_phase()
153 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT); in mp2975_read_phase()
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H A Dir35221.c25 int phase, int reg) in ir35221_read_word_data() argument
31 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
35 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
39 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
43 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
47 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
51 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
55 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
59 ret = pmbus_read_word_data(client, page, phase, in ir35221_read_word_data()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c176 int phase; in dcss_scaler_gaussian_filter() local
181 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
182 coef[phase][0] = 0; in dcss_scaler_gaussian_filter()
183 coef[phase][PSC_NUM_TAPS - 1] = 0; in dcss_scaler_gaussian_filter()
223 /* override phase 0 with identity filter if specified */ in dcss_scaler_gaussian_filter()
230 for (phase = 0; phase < PSC_STORED_PHASES; phase++) { in dcss_scaler_gaussian_filter()
235 sum += coef[phase][i]; in dcss_scaler_gaussian_filter()
237 ll_temp = coef[phase][i]; in dcss_scaler_gaussian_filter()
241 coef[phase][i] = (int)ll_temp; in dcss_scaler_gaussian_filter()
251 * @use_5_taps: 0 for 7 taps per phase, 1 for 5 taps
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/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-sirf.c77 int phase; in sdhci_sirf_execute_tuning() local
88 phase = 0; in sdhci_sirf_execute_tuning()
92 clock_setting | phase, in sdhci_sirf_execute_tuning()
98 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", in sdhci_sirf_execute_tuning()
99 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
101 start = phase; in sdhci_sirf_execute_tuning()
102 end = phase; in sdhci_sirf_execute_tuning()
104 if (phase == (SIRF_TUNING_COUNT - 1) in sdhci_sirf_execute_tuning()
108 dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n", in sdhci_sirf_execute_tuning()
109 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
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H A Ddw_mmc-rockchip.c77 * Set the drive phase offset based on speed mode to achieve hold times. in dw_mci_rk3288_set_ios()
103 int phase; in dw_mci_rk3288_set_ios() local
106 * In almost all cases a 90 degree phase offset will provide in dw_mci_rk3288_set_ios()
111 phase = 90; in dw_mci_rk3288_set_ios()
117 * bus width is 8 we need to double the phase offset in dw_mci_rk3288_set_ios()
121 phase = 180; in dw_mci_rk3288_set_ios()
133 phase = 180; in dw_mci_rk3288_set_ios()
137 clk_set_phase(priv->drv_clk, phase); in dw_mci_rk3288_set_ios()
165 * one phase from degree list and loop around until we get one. in dw_mci_v2_execute_tuning()
166 * It's impossible all 4 fixed phase won't be able to work. in dw_mci_v2_execute_tuning()
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/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Dclk-phase.c11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_get_phase() local
43 val = meson_parm_read(clk->map, &phase->ph); in meson_clk_phase_get_phase()
45 return meson_clk_degrees_from_val(val, phase->ph.width); in meson_clk_phase_get_phase()
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); in meson_clk_phase_set_phase() local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width); in meson_clk_phase_set_phase()
55 meson_parm_write(clk->map, &phase->ph, val); in meson_clk_phase_set_phase()
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase 0 and sync it to phase 1 and 2 */ in meson_clk_triphase_sync()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/tidss/
H A Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) argument
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) argument
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) argument
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) argument
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) argument
132 #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) argument
135 #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) argument
137 #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) argument
/OK3568_Linux_fs/kernel/drivers/char/
H A Dppdev.c20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
397 pp->saved_state.phase = info->phase; in pp_do_ioctl()
399 info->phase = pp->state.phase; in pp_do_ioctl()
428 pp->state.phase = init_phase(mode); in pp_do_ioctl()
432 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
452 int phase; in pp_do_ioctl() local
454 if (copy_from_user(&phase, argp, sizeof(phase))) in pp_do_ioctl()
457 /* FIXME: validate phase */ in pp_do_ioctl()
458 pp->state.phase = phase; in pp_do_ioctl()
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/OK3568_Linux_fs/kernel/drivers/media/i2c/
H A Dsaa711x_regs.h112 /* Horizontal phase scaling */
159 /* Horizontal phase scaling */
422 /* Task A: Horizontal phase scaling */
426 "Task A: Horizontal luminance phase offset"},
431 "Task A: Horizontal chrominance phase offset"},
443 "Task A: Vertical chrominance phase offset '00'"},
445 "Task A: Vertical chrominance phase offset '01'"},
447 "Task A: Vertical chrominance phase offset '10'"},
449 "Task A: Vertical chrominance phase offset '11'"},
451 "Task A: Vertical luminance phase offset '00'"},
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
/OK3568_Linux_fs/kernel/drivers/scsi/
H A DNCR5380.c74 * phase goes through the various phases as instructed by the target.
261 {BASR_PHASE_MATCH, "PHASE MATCH"},
340 * NCR5380_print_phase - show SCSI phase
343 * Print the current SCSI phase for debugging purposes
354 shost_printk(KERN_DEBUG, instance, "REQ not asserted, phase unknown.\n"); in NCR5380_print_phase()
359 shost_printk(KERN_DEBUG, instance, "phase %s\n", phases[i].name); in NCR5380_print_phase()
464 * the SCSI bus busy. Check for BUS FREE phase. If not, try to abort the
749 * Called by the interrupt handler when DMA finishes or a phase
763 p = hostdata->connected->SCp.phase; in NCR5380_dma_complete()
787 pr_err("scsi%d: bus stuck in data phase -- probably a single byte overrun!\n", in NCR5380_dma_complete()
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/OK3568_Linux_fs/buildroot/dl/sox/git/src/
H A Dsynth.c89 double offset, phase; member
230 NUMERIC_PARAMETER(phase , 0, 100) in getopts()
302 NUMERIC_PARAMETER(phase , 0, 100) in getopts()
381 do d2 = d1 + (chan->phase? DRANQD1:dranqd1(r)) * colour; in start()
434 "offset=%g, phase=%g, p1=%g, p2=%g, p3=%g mult=%g", in start()
438 chan->offset, chan->phase, chan->p1, chan->p2, chan->p3, chan->mult); in start()
463 if (chan->type < synth_noise) { /* Need to calculate phase: */ in flow()
464 double phase; /* [0, 1) */ in flow() local
467 phase = (chan->freq + p->samples_done * chan->mult) * in flow()
471 phase = (chan->freq + sign(chan->mult) * in flow()
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/OK3568_Linux_fs/kernel/include/trace/events/
H A Dclk.h156 TP_PROTO(struct clk_core *core, int phase),
158 TP_ARGS(core, phase),
162 __field( int, phase )
167 __entry->phase = phase;
170 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
175 TP_PROTO(struct clk_core *core, int phase),
177 TP_ARGS(core, phase)
182 TP_PROTO(struct clk_core *core, int phase),
184 TP_ARGS(core, phase)
/OK3568_Linux_fs/kernel/drivers/staging/iio/Documentation/
H A Dsysfs-bus-iio-dds36 Stores phase into Y.
38 allows for pin controlled PSK Phase Shift Keying
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
/OK3568_Linux_fs/kernel/drivers/char/ipmi/
H A Dkcs_bmc.c90 kcs_bmc->phase = KCS_PHASE_ERROR; in kcs_force_abort()
99 switch (kcs_bmc->phase) { in kcs_bmc_handle_data()
101 kcs_bmc->phase = KCS_PHASE_WRITE_DATA; in kcs_bmc_handle_data()
121 kcs_bmc->phase = KCS_PHASE_WRITE_DONE; in kcs_bmc_handle_data()
143 kcs_bmc->phase = KCS_PHASE_IDLE; in kcs_bmc_handle_data()
155 kcs_bmc->phase = KCS_PHASE_ABORT_ERROR2; in kcs_bmc_handle_data()
162 kcs_bmc->phase = KCS_PHASE_IDLE; in kcs_bmc_handle_data()
181 kcs_bmc->phase = KCS_PHASE_WRITE_START; in kcs_bmc_handle_cmd()
188 if (kcs_bmc->phase != KCS_PHASE_WRITE_DATA) { in kcs_bmc_handle_cmd()
193 kcs_bmc->phase = KCS_PHASE_WRITE_END_CMD; in kcs_bmc_handle_cmd()
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/OK3568_Linux_fs/yocto/meta-openembedded/meta-networking/recipes-support/stunnel/stunnel/
H A Dfix-openssl-no-des.patch38 @@ -66,7 +66,7 @@ NOEXPORT char *nntp_client(CLI *, SERVICE_OPTIONS *, const PHASE);
39 NOEXPORT char *ldap_client(CLI *, SERVICE_OPTIONS *, const PHASE);
40 NOEXPORT char *connect_server(CLI *, SERVICE_OPTIONS *, const PHASE);
41 NOEXPORT char *connect_client(CLI *, SERVICE_OPTIONS *, const PHASE);
47 @@ -1351,7 +1351,7 @@ NOEXPORT char *connect_client(CLI *c, SERVICE_OPTIONS *opt, const PHASE phase…
56 @@ -1395,7 +1395,7 @@ NOEXPORT char *connect_client(CLI *c, SERVICE_OPTIONS *opt, const PHASE phase…
/OK3568_Linux_fs/kernel/Documentation/driver-api/pm/
H A Ddevices.rst234 always go together, and both are multi-phase operations.
271 sleep states and the hibernation state ("suspend-to-disk"). Each phase involves
272 executing callbacks for every device before the next phase begins. Not all
285 rules are used to determine which callback to execute in the given phase:
318 1. The ``prepare`` phase is meant to prevent races by preventing new
323 suspend-related phases, during the ``prepare`` phase the device
393 4. The ``suspend_noirq`` phase occurs after IRQ handlers have been disabled,
402 an error during the suspend phase by fielding a shared interrupt
432 generally means undoing the actions of the ``suspend_noirq`` phase. If
446 the preceding ``suspend_late`` phase.
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/OK3568_Linux_fs/kernel/drivers/scsi/pcmcia/
H A Dnsp_cs.c229 SCpnt->SCp.phase = PH_UNDETERMINED; in nsp_queuecommand_lck()
237 SCp.phase : current state of the command */ in nsp_queuecommand_lck()
361 * Start selection phase
370 unsigned char phase, arbit; in nsphw_start_selection() local
374 phase = nsp_index_read(base, SCSIBUSMON); in nsphw_start_selection()
375 if(phase != BUSMON_BUS_FREE) { in nsphw_start_selection()
382 SCpnt->SCp.phase = PH_ARBSTART; in nsphw_start_selection()
402 SCpnt->SCp.phase = PH_SELSTART; in nsphw_start_selection()
513 * wait for bus phase change
549 unsigned char phase, i_src; in nsp_expect_signal() local
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