1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2020 Nvidia Technologies Ltd.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include "pmbus.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* Vendor specific registers. */
16*4882a593Smuzhiyun #define MP2975_MFR_APS_HYS_R2 0x0d
17*4882a593Smuzhiyun #define MP2975_MFR_SLOPE_TRIM3 0x1d
18*4882a593Smuzhiyun #define MP2975_MFR_VR_MULTI_CONFIG_R1 0x0d
19*4882a593Smuzhiyun #define MP2975_MFR_VR_MULTI_CONFIG_R2 0x1d
20*4882a593Smuzhiyun #define MP2975_MFR_APS_DECAY_ADV 0x56
21*4882a593Smuzhiyun #define MP2975_MFR_DC_LOOP_CTRL 0x59
22*4882a593Smuzhiyun #define MP2975_MFR_OCP_UCP_PHASE_SET 0x65
23*4882a593Smuzhiyun #define MP2975_MFR_VR_CONFIG1 0x68
24*4882a593Smuzhiyun #define MP2975_MFR_READ_CS1_2 0x82
25*4882a593Smuzhiyun #define MP2975_MFR_READ_CS3_4 0x83
26*4882a593Smuzhiyun #define MP2975_MFR_READ_CS5_6 0x84
27*4882a593Smuzhiyun #define MP2975_MFR_READ_CS7_8 0x85
28*4882a593Smuzhiyun #define MP2975_MFR_READ_CS9_10 0x86
29*4882a593Smuzhiyun #define MP2975_MFR_READ_CS11_12 0x87
30*4882a593Smuzhiyun #define MP2975_MFR_READ_IOUT_PK 0x90
31*4882a593Smuzhiyun #define MP2975_MFR_READ_POUT_PK 0x91
32*4882a593Smuzhiyun #define MP2975_MFR_READ_VREF_R1 0xa1
33*4882a593Smuzhiyun #define MP2975_MFR_READ_VREF_R2 0xa3
34*4882a593Smuzhiyun #define MP2975_MFR_OVP_TH_SET 0xe5
35*4882a593Smuzhiyun #define MP2975_MFR_UVP_SET 0xe6
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define MP2975_VOUT_FORMAT BIT(15)
38*4882a593Smuzhiyun #define MP2975_VID_STEP_SEL_R1 BIT(4)
39*4882a593Smuzhiyun #define MP2975_IMVP9_EN_R1 BIT(13)
40*4882a593Smuzhiyun #define MP2975_VID_STEP_SEL_R2 BIT(3)
41*4882a593Smuzhiyun #define MP2975_IMVP9_EN_R2 BIT(12)
42*4882a593Smuzhiyun #define MP2975_PRT_THRES_DIV_OV_EN BIT(14)
43*4882a593Smuzhiyun #define MP2975_DRMOS_KCS GENMASK(13, 12)
44*4882a593Smuzhiyun #define MP2975_PROT_DEV_OV_OFF 10
45*4882a593Smuzhiyun #define MP2975_PROT_DEV_OV_ON 5
46*4882a593Smuzhiyun #define MP2975_SENSE_AMPL BIT(11)
47*4882a593Smuzhiyun #define MP2975_SENSE_AMPL_UNIT 1
48*4882a593Smuzhiyun #define MP2975_SENSE_AMPL_HALF 2
49*4882a593Smuzhiyun #define MP2975_VIN_UV_LIMIT_UNIT 8
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define MP2975_MAX_PHASE_RAIL1 8
52*4882a593Smuzhiyun #define MP2975_MAX_PHASE_RAIL2 4
53*4882a593Smuzhiyun #define MP2975_PAGE_NUM 2
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define MP2975_RAIL2_FUNC (PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | \
56*4882a593Smuzhiyun PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | \
57*4882a593Smuzhiyun PMBUS_HAVE_POUT | PMBUS_PHASE_VIRTUAL)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun struct mp2975_data {
60*4882a593Smuzhiyun struct pmbus_driver_info info;
61*4882a593Smuzhiyun int vout_scale;
62*4882a593Smuzhiyun int vid_step[MP2975_PAGE_NUM];
63*4882a593Smuzhiyun int vref[MP2975_PAGE_NUM];
64*4882a593Smuzhiyun int vref_off[MP2975_PAGE_NUM];
65*4882a593Smuzhiyun int vout_max[MP2975_PAGE_NUM];
66*4882a593Smuzhiyun int vout_ov_fixed[MP2975_PAGE_NUM];
67*4882a593Smuzhiyun int vout_format[MP2975_PAGE_NUM];
68*4882a593Smuzhiyun int curr_sense_gain[MP2975_PAGE_NUM];
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define to_mp2975_data(x) container_of(x, struct mp2975_data, info)
72*4882a593Smuzhiyun
mp2975_read_byte_data(struct i2c_client * client,int page,int reg)73*4882a593Smuzhiyun static int mp2975_read_byte_data(struct i2c_client *client, int page, int reg)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun switch (reg) {
76*4882a593Smuzhiyun case PMBUS_VOUT_MODE:
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * Enforce VOUT direct format, since device allows to set the
79*4882a593Smuzhiyun * different formats for the different rails. Conversion from
80*4882a593Smuzhiyun * VID to direct provided by driver internally, in case it is
81*4882a593Smuzhiyun * necessary.
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun return PB_VOUT_MODE_DIRECT;
84*4882a593Smuzhiyun default:
85*4882a593Smuzhiyun return -ENODATA;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static int
mp2975_read_word_helper(struct i2c_client * client,int page,int phase,u8 reg,u16 mask)90*4882a593Smuzhiyun mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg,
91*4882a593Smuzhiyun u16 mask)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun int ret = pmbus_read_word_data(client, page, phase, reg);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return (ret > 0) ? ret & mask : ret;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static int
mp2975_vid2direct(int vrf,int val)99*4882a593Smuzhiyun mp2975_vid2direct(int vrf, int val)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun switch (vrf) {
102*4882a593Smuzhiyun case vr12:
103*4882a593Smuzhiyun if (val >= 0x01)
104*4882a593Smuzhiyun return 250 + (val - 1) * 5;
105*4882a593Smuzhiyun break;
106*4882a593Smuzhiyun case vr13:
107*4882a593Smuzhiyun if (val >= 0x01)
108*4882a593Smuzhiyun return 500 + (val - 1) * 10;
109*4882a593Smuzhiyun break;
110*4882a593Smuzhiyun case imvp9:
111*4882a593Smuzhiyun if (val >= 0x01)
112*4882a593Smuzhiyun return 200 + (val - 1) * 10;
113*4882a593Smuzhiyun break;
114*4882a593Smuzhiyun default:
115*4882a593Smuzhiyun return -EINVAL;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun return 0;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static int
mp2975_read_phase(struct i2c_client * client,struct mp2975_data * data,int page,int phase,u8 reg)121*4882a593Smuzhiyun mp2975_read_phase(struct i2c_client *client, struct mp2975_data *data,
122*4882a593Smuzhiyun int page, int phase, u8 reg)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun int ph_curr, ret;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun ret = pmbus_read_word_data(client, page, phase, reg);
127*4882a593Smuzhiyun if (ret < 0)
128*4882a593Smuzhiyun return ret;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (!((phase + 1) % MP2975_PAGE_NUM))
131*4882a593Smuzhiyun ret >>= 8;
132*4882a593Smuzhiyun ret &= 0xff;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun * Output value is calculated as: (READ_CSx / 80 – 1.23) / (Kcs * Rcs)
136*4882a593Smuzhiyun * where:
137*4882a593Smuzhiyun * - Kcs is the DrMOS current sense gain of power stage, which is
138*4882a593Smuzhiyun * obtained from the register MP2975_MFR_VR_CONFIG1, bits 13-12 with
139*4882a593Smuzhiyun * the following selection of DrMOS (data->curr_sense_gain[page]):
140*4882a593Smuzhiyun * 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A.
141*4882a593Smuzhiyun * - Rcs is the internal phase current sense resistor which is constant
142*4882a593Smuzhiyun * value 1kΩ.
143*4882a593Smuzhiyun */
144*4882a593Smuzhiyun ph_curr = ret * 100 - 9800;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * Current phase sensing, providing by the device is not accurate
148*4882a593Smuzhiyun * for the light load. This because sampling of current occurrence of
149*4882a593Smuzhiyun * bit weight has a big deviation for light load. For handling such
150*4882a593Smuzhiyun * case phase current is represented as the maximum between the value
151*4882a593Smuzhiyun * calculated above and total rail current divided by number phases.
152*4882a593Smuzhiyun */
153*4882a593Smuzhiyun ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOUT);
154*4882a593Smuzhiyun if (ret < 0)
155*4882a593Smuzhiyun return ret;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun return max_t(int, DIV_ROUND_CLOSEST(ret, data->info.phases[page]),
158*4882a593Smuzhiyun DIV_ROUND_CLOSEST(ph_curr, data->curr_sense_gain[page]));
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun static int
mp2975_read_phases(struct i2c_client * client,struct mp2975_data * data,int page,int phase)162*4882a593Smuzhiyun mp2975_read_phases(struct i2c_client *client, struct mp2975_data *data,
163*4882a593Smuzhiyun int page, int phase)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun int ret;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun if (page) {
168*4882a593Smuzhiyun switch (phase) {
169*4882a593Smuzhiyun case 0 ... 1:
170*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
171*4882a593Smuzhiyun MP2975_MFR_READ_CS7_8);
172*4882a593Smuzhiyun break;
173*4882a593Smuzhiyun case 2 ... 3:
174*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
175*4882a593Smuzhiyun MP2975_MFR_READ_CS9_10);
176*4882a593Smuzhiyun break;
177*4882a593Smuzhiyun case 4 ... 5:
178*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
179*4882a593Smuzhiyun MP2975_MFR_READ_CS11_12);
180*4882a593Smuzhiyun break;
181*4882a593Smuzhiyun default:
182*4882a593Smuzhiyun return -ENODATA;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun } else {
185*4882a593Smuzhiyun switch (phase) {
186*4882a593Smuzhiyun case 0 ... 1:
187*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
188*4882a593Smuzhiyun MP2975_MFR_READ_CS1_2);
189*4882a593Smuzhiyun break;
190*4882a593Smuzhiyun case 2 ... 3:
191*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
192*4882a593Smuzhiyun MP2975_MFR_READ_CS3_4);
193*4882a593Smuzhiyun break;
194*4882a593Smuzhiyun case 4 ... 5:
195*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
196*4882a593Smuzhiyun MP2975_MFR_READ_CS5_6);
197*4882a593Smuzhiyun break;
198*4882a593Smuzhiyun case 6 ... 7:
199*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
200*4882a593Smuzhiyun MP2975_MFR_READ_CS7_8);
201*4882a593Smuzhiyun break;
202*4882a593Smuzhiyun case 8 ... 9:
203*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
204*4882a593Smuzhiyun MP2975_MFR_READ_CS9_10);
205*4882a593Smuzhiyun break;
206*4882a593Smuzhiyun case 10 ... 11:
207*4882a593Smuzhiyun ret = mp2975_read_phase(client, data, page, phase,
208*4882a593Smuzhiyun MP2975_MFR_READ_CS11_12);
209*4882a593Smuzhiyun break;
210*4882a593Smuzhiyun default:
211*4882a593Smuzhiyun return -ENODATA;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun return ret;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
mp2975_read_word_data(struct i2c_client * client,int page,int phase,int reg)217*4882a593Smuzhiyun static int mp2975_read_word_data(struct i2c_client *client, int page,
218*4882a593Smuzhiyun int phase, int reg)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun const struct pmbus_driver_info *info = pmbus_get_driver_info(client);
221*4882a593Smuzhiyun struct mp2975_data *data = to_mp2975_data(info);
222*4882a593Smuzhiyun int ret;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun switch (reg) {
225*4882a593Smuzhiyun case PMBUS_OT_FAULT_LIMIT:
226*4882a593Smuzhiyun ret = mp2975_read_word_helper(client, page, phase, reg,
227*4882a593Smuzhiyun GENMASK(7, 0));
228*4882a593Smuzhiyun break;
229*4882a593Smuzhiyun case PMBUS_VIN_OV_FAULT_LIMIT:
230*4882a593Smuzhiyun ret = mp2975_read_word_helper(client, page, phase, reg,
231*4882a593Smuzhiyun GENMASK(7, 0));
232*4882a593Smuzhiyun if (ret < 0)
233*4882a593Smuzhiyun return ret;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun ret = DIV_ROUND_CLOSEST(ret, MP2975_VIN_UV_LIMIT_UNIT);
236*4882a593Smuzhiyun break;
237*4882a593Smuzhiyun case PMBUS_VOUT_OV_FAULT_LIMIT:
238*4882a593Smuzhiyun /*
239*4882a593Smuzhiyun * Register provides two values for over-voltage protection
240*4882a593Smuzhiyun * threshold for fixed (ovp2) and tracking (ovp1) modes. The
241*4882a593Smuzhiyun * minimum of these two values is provided as over-voltage
242*4882a593Smuzhiyun * fault alarm.
243*4882a593Smuzhiyun */
244*4882a593Smuzhiyun ret = mp2975_read_word_helper(client, page, phase,
245*4882a593Smuzhiyun MP2975_MFR_OVP_TH_SET,
246*4882a593Smuzhiyun GENMASK(2, 0));
247*4882a593Smuzhiyun if (ret < 0)
248*4882a593Smuzhiyun return ret;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun ret = min_t(int, data->vout_max[page] + 50 * (ret + 1),
251*4882a593Smuzhiyun data->vout_ov_fixed[page]);
252*4882a593Smuzhiyun break;
253*4882a593Smuzhiyun case PMBUS_VOUT_UV_FAULT_LIMIT:
254*4882a593Smuzhiyun ret = mp2975_read_word_helper(client, page, phase,
255*4882a593Smuzhiyun MP2975_MFR_UVP_SET,
256*4882a593Smuzhiyun GENMASK(2, 0));
257*4882a593Smuzhiyun if (ret < 0)
258*4882a593Smuzhiyun return ret;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun ret = DIV_ROUND_CLOSEST(data->vref[page] * 10 - 50 *
261*4882a593Smuzhiyun (ret + 1) * data->vout_scale, 10);
262*4882a593Smuzhiyun break;
263*4882a593Smuzhiyun case PMBUS_READ_VOUT:
264*4882a593Smuzhiyun ret = mp2975_read_word_helper(client, page, phase, reg,
265*4882a593Smuzhiyun GENMASK(11, 0));
266*4882a593Smuzhiyun if (ret < 0)
267*4882a593Smuzhiyun return ret;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /*
270*4882a593Smuzhiyun * READ_VOUT can be provided in VID or direct format. The
271*4882a593Smuzhiyun * format type is specified by bit 15 of the register
272*4882a593Smuzhiyun * MP2975_MFR_DC_LOOP_CTRL. The driver enforces VOUT direct
273*4882a593Smuzhiyun * format, since device allows to set the different formats for
274*4882a593Smuzhiyun * the different rails and also all VOUT limits registers are
275*4882a593Smuzhiyun * provided in a direct format. In case format is VID - convert
276*4882a593Smuzhiyun * to direct.
277*4882a593Smuzhiyun */
278*4882a593Smuzhiyun if (data->vout_format[page] == vid)
279*4882a593Smuzhiyun ret = mp2975_vid2direct(info->vrm_version[page], ret);
280*4882a593Smuzhiyun break;
281*4882a593Smuzhiyun case PMBUS_VIRT_READ_POUT_MAX:
282*4882a593Smuzhiyun ret = mp2975_read_word_helper(client, page, phase,
283*4882a593Smuzhiyun MP2975_MFR_READ_POUT_PK,
284*4882a593Smuzhiyun GENMASK(12, 0));
285*4882a593Smuzhiyun if (ret < 0)
286*4882a593Smuzhiyun return ret;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun ret = DIV_ROUND_CLOSEST(ret, 4);
289*4882a593Smuzhiyun break;
290*4882a593Smuzhiyun case PMBUS_VIRT_READ_IOUT_MAX:
291*4882a593Smuzhiyun ret = mp2975_read_word_helper(client, page, phase,
292*4882a593Smuzhiyun MP2975_MFR_READ_IOUT_PK,
293*4882a593Smuzhiyun GENMASK(12, 0));
294*4882a593Smuzhiyun if (ret < 0)
295*4882a593Smuzhiyun return ret;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun ret = DIV_ROUND_CLOSEST(ret, 4);
298*4882a593Smuzhiyun break;
299*4882a593Smuzhiyun case PMBUS_READ_IOUT:
300*4882a593Smuzhiyun ret = mp2975_read_phases(client, data, page, phase);
301*4882a593Smuzhiyun if (ret < 0)
302*4882a593Smuzhiyun return ret;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun break;
305*4882a593Smuzhiyun case PMBUS_UT_WARN_LIMIT:
306*4882a593Smuzhiyun case PMBUS_UT_FAULT_LIMIT:
307*4882a593Smuzhiyun case PMBUS_VIN_UV_WARN_LIMIT:
308*4882a593Smuzhiyun case PMBUS_VIN_UV_FAULT_LIMIT:
309*4882a593Smuzhiyun case PMBUS_VOUT_UV_WARN_LIMIT:
310*4882a593Smuzhiyun case PMBUS_VOUT_OV_WARN_LIMIT:
311*4882a593Smuzhiyun case PMBUS_VIN_OV_WARN_LIMIT:
312*4882a593Smuzhiyun case PMBUS_IIN_OC_FAULT_LIMIT:
313*4882a593Smuzhiyun case PMBUS_IOUT_OC_LV_FAULT_LIMIT:
314*4882a593Smuzhiyun case PMBUS_IIN_OC_WARN_LIMIT:
315*4882a593Smuzhiyun case PMBUS_IOUT_OC_WARN_LIMIT:
316*4882a593Smuzhiyun case PMBUS_IOUT_OC_FAULT_LIMIT:
317*4882a593Smuzhiyun case PMBUS_IOUT_UC_FAULT_LIMIT:
318*4882a593Smuzhiyun case PMBUS_POUT_OP_FAULT_LIMIT:
319*4882a593Smuzhiyun case PMBUS_POUT_OP_WARN_LIMIT:
320*4882a593Smuzhiyun case PMBUS_PIN_OP_WARN_LIMIT:
321*4882a593Smuzhiyun return -ENXIO;
322*4882a593Smuzhiyun default:
323*4882a593Smuzhiyun return -ENODATA;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun return ret;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
mp2975_identify_multiphase_rail2(struct i2c_client * client)329*4882a593Smuzhiyun static int mp2975_identify_multiphase_rail2(struct i2c_client *client)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun int ret;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /*
334*4882a593Smuzhiyun * Identify multiphase for rail 2 - could be from 0 to 4.
335*4882a593Smuzhiyun * In case phase number is zero – only page zero is supported
336*4882a593Smuzhiyun */
337*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 2);
338*4882a593Smuzhiyun if (ret < 0)
339*4882a593Smuzhiyun return ret;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /* Identify multiphase for rail 2 - could be from 0 to 4. */
342*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, MP2975_MFR_VR_MULTI_CONFIG_R2);
343*4882a593Smuzhiyun if (ret < 0)
344*4882a593Smuzhiyun return ret;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun ret &= GENMASK(2, 0);
347*4882a593Smuzhiyun return (ret >= 4) ? 4 : ret;
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
mp2975_set_phase_rail1(struct pmbus_driver_info * info)350*4882a593Smuzhiyun static void mp2975_set_phase_rail1(struct pmbus_driver_info *info)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun int i;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun for (i = 0 ; i < info->phases[0]; i++)
355*4882a593Smuzhiyun info->pfunc[i] = PMBUS_HAVE_IOUT;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun static void
mp2975_set_phase_rail2(struct pmbus_driver_info * info,int num_phases)359*4882a593Smuzhiyun mp2975_set_phase_rail2(struct pmbus_driver_info *info, int num_phases)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun int i;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun /* Set phases for rail 2 from upper to lower. */
364*4882a593Smuzhiyun for (i = 1; i <= num_phases; i++)
365*4882a593Smuzhiyun info->pfunc[MP2975_MAX_PHASE_RAIL1 - i] = PMBUS_HAVE_IOUT;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun static int
mp2975_identify_multiphase(struct i2c_client * client,struct mp2975_data * data,struct pmbus_driver_info * info)369*4882a593Smuzhiyun mp2975_identify_multiphase(struct i2c_client *client, struct mp2975_data *data,
370*4882a593Smuzhiyun struct pmbus_driver_info *info)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun int num_phases2, ret;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 2);
375*4882a593Smuzhiyun if (ret < 0)
376*4882a593Smuzhiyun return ret;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* Identify multiphase for rail 1 - could be from 1 to 8. */
379*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, MP2975_MFR_VR_MULTI_CONFIG_R1);
380*4882a593Smuzhiyun if (ret <= 0)
381*4882a593Smuzhiyun return ret;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun info->phases[0] = ret & GENMASK(3, 0);
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun /*
386*4882a593Smuzhiyun * The device provides a total of 8 PWM pins, and can be configured
387*4882a593Smuzhiyun * to different phase count applications for rail 1 and rail 2.
388*4882a593Smuzhiyun * Rail 1 can be set to 8 phases, while rail 2 can only be set to 4
389*4882a593Smuzhiyun * phases at most. When rail 1’s phase count is configured as 0, rail
390*4882a593Smuzhiyun * 1 operates with 1-phase DCM. When rail 2 phase count is configured
391*4882a593Smuzhiyun * as 0, rail 2 is disabled.
392*4882a593Smuzhiyun */
393*4882a593Smuzhiyun if (info->phases[0] > MP2975_MAX_PHASE_RAIL1)
394*4882a593Smuzhiyun return -EINVAL;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun mp2975_set_phase_rail1(info);
397*4882a593Smuzhiyun num_phases2 = min(MP2975_MAX_PHASE_RAIL1 - info->phases[0],
398*4882a593Smuzhiyun MP2975_MAX_PHASE_RAIL2);
399*4882a593Smuzhiyun if (info->phases[1] && info->phases[1] <= num_phases2)
400*4882a593Smuzhiyun mp2975_set_phase_rail2(info, num_phases2);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun return 0;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun static int
mp2975_identify_vid(struct i2c_client * client,struct mp2975_data * data,struct pmbus_driver_info * info,u32 reg,int page,u32 imvp_bit,u32 vr_bit)406*4882a593Smuzhiyun mp2975_identify_vid(struct i2c_client *client, struct mp2975_data *data,
407*4882a593Smuzhiyun struct pmbus_driver_info *info, u32 reg, int page,
408*4882a593Smuzhiyun u32 imvp_bit, u32 vr_bit)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun int ret;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun /* Identify VID mode and step selection. */
413*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, reg);
414*4882a593Smuzhiyun if (ret < 0)
415*4882a593Smuzhiyun return ret;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun if (ret & imvp_bit) {
418*4882a593Smuzhiyun info->vrm_version[page] = imvp9;
419*4882a593Smuzhiyun data->vid_step[page] = MP2975_PROT_DEV_OV_OFF;
420*4882a593Smuzhiyun } else if (ret & vr_bit) {
421*4882a593Smuzhiyun info->vrm_version[page] = vr12;
422*4882a593Smuzhiyun data->vid_step[page] = MP2975_PROT_DEV_OV_ON;
423*4882a593Smuzhiyun } else {
424*4882a593Smuzhiyun info->vrm_version[page] = vr13;
425*4882a593Smuzhiyun data->vid_step[page] = MP2975_PROT_DEV_OV_OFF;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun return 0;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun static int
mp2975_identify_rails_vid(struct i2c_client * client,struct mp2975_data * data,struct pmbus_driver_info * info)432*4882a593Smuzhiyun mp2975_identify_rails_vid(struct i2c_client *client, struct mp2975_data *data,
433*4882a593Smuzhiyun struct pmbus_driver_info *info)
434*4882a593Smuzhiyun {
435*4882a593Smuzhiyun int ret;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 2);
438*4882a593Smuzhiyun if (ret < 0)
439*4882a593Smuzhiyun return ret;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun /* Identify VID mode for rail 1. */
442*4882a593Smuzhiyun ret = mp2975_identify_vid(client, data, info,
443*4882a593Smuzhiyun MP2975_MFR_VR_MULTI_CONFIG_R1, 0,
444*4882a593Smuzhiyun MP2975_IMVP9_EN_R1, MP2975_VID_STEP_SEL_R1);
445*4882a593Smuzhiyun if (ret < 0)
446*4882a593Smuzhiyun return ret;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun /* Identify VID mode for rail 2, if connected. */
449*4882a593Smuzhiyun if (info->phases[1])
450*4882a593Smuzhiyun ret = mp2975_identify_vid(client, data, info,
451*4882a593Smuzhiyun MP2975_MFR_VR_MULTI_CONFIG_R2, 1,
452*4882a593Smuzhiyun MP2975_IMVP9_EN_R2,
453*4882a593Smuzhiyun MP2975_VID_STEP_SEL_R2);
454*4882a593Smuzhiyun return ret;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun static int
mp2975_current_sense_gain_get(struct i2c_client * client,struct mp2975_data * data)458*4882a593Smuzhiyun mp2975_current_sense_gain_get(struct i2c_client *client,
459*4882a593Smuzhiyun struct mp2975_data *data)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun int i, ret;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun /*
464*4882a593Smuzhiyun * Obtain DrMOS current sense gain of power stage from the register
465*4882a593Smuzhiyun * MP2975_MFR_VR_CONFIG1, bits 13-12. The value is selected as below:
466*4882a593Smuzhiyun * 00b - 5µA/A, 01b - 8.5µA/A, 10b - 9.7µA/A, 11b - 10µA/A. Other
467*4882a593Smuzhiyun * values are invalid.
468*4882a593Smuzhiyun */
469*4882a593Smuzhiyun for (i = 0 ; i < data->info.pages; i++) {
470*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, i);
471*4882a593Smuzhiyun if (ret < 0)
472*4882a593Smuzhiyun return ret;
473*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client,
474*4882a593Smuzhiyun MP2975_MFR_VR_CONFIG1);
475*4882a593Smuzhiyun if (ret < 0)
476*4882a593Smuzhiyun return ret;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun switch ((ret & MP2975_DRMOS_KCS) >> 12) {
479*4882a593Smuzhiyun case 0:
480*4882a593Smuzhiyun data->curr_sense_gain[i] = 50;
481*4882a593Smuzhiyun break;
482*4882a593Smuzhiyun case 1:
483*4882a593Smuzhiyun data->curr_sense_gain[i] = 85;
484*4882a593Smuzhiyun break;
485*4882a593Smuzhiyun case 2:
486*4882a593Smuzhiyun data->curr_sense_gain[i] = 97;
487*4882a593Smuzhiyun break;
488*4882a593Smuzhiyun default:
489*4882a593Smuzhiyun data->curr_sense_gain[i] = 100;
490*4882a593Smuzhiyun break;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun return 0;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun static int
mp2975_vref_get(struct i2c_client * client,struct mp2975_data * data,struct pmbus_driver_info * info)498*4882a593Smuzhiyun mp2975_vref_get(struct i2c_client *client, struct mp2975_data *data,
499*4882a593Smuzhiyun struct pmbus_driver_info *info)
500*4882a593Smuzhiyun {
501*4882a593Smuzhiyun int ret;
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 3);
504*4882a593Smuzhiyun if (ret < 0)
505*4882a593Smuzhiyun return ret;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun /* Get voltage reference value for rail 1. */
508*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, MP2975_MFR_READ_VREF_R1);
509*4882a593Smuzhiyun if (ret < 0)
510*4882a593Smuzhiyun return ret;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun data->vref[0] = ret * data->vid_step[0];
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun /* Get voltage reference value for rail 2, if connected. */
515*4882a593Smuzhiyun if (data->info.pages == MP2975_PAGE_NUM) {
516*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, MP2975_MFR_READ_VREF_R2);
517*4882a593Smuzhiyun if (ret < 0)
518*4882a593Smuzhiyun return ret;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun data->vref[1] = ret * data->vid_step[1];
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun static int
mp2975_vref_offset_get(struct i2c_client * client,struct mp2975_data * data,int page)526*4882a593Smuzhiyun mp2975_vref_offset_get(struct i2c_client *client, struct mp2975_data *data,
527*4882a593Smuzhiyun int page)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun int ret;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, MP2975_MFR_OVP_TH_SET);
532*4882a593Smuzhiyun if (ret < 0)
533*4882a593Smuzhiyun return ret;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun switch ((ret & GENMASK(5, 3)) >> 3) {
536*4882a593Smuzhiyun case 1:
537*4882a593Smuzhiyun data->vref_off[page] = 140;
538*4882a593Smuzhiyun break;
539*4882a593Smuzhiyun case 2:
540*4882a593Smuzhiyun data->vref_off[page] = 220;
541*4882a593Smuzhiyun break;
542*4882a593Smuzhiyun case 4:
543*4882a593Smuzhiyun data->vref_off[page] = 400;
544*4882a593Smuzhiyun break;
545*4882a593Smuzhiyun default:
546*4882a593Smuzhiyun return -EINVAL;
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun return 0;
549*4882a593Smuzhiyun }
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun static int
mp2975_vout_max_get(struct i2c_client * client,struct mp2975_data * data,struct pmbus_driver_info * info,int page)552*4882a593Smuzhiyun mp2975_vout_max_get(struct i2c_client *client, struct mp2975_data *data,
553*4882a593Smuzhiyun struct pmbus_driver_info *info, int page)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun int ret;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun /* Get maximum reference voltage of VID-DAC in VID format. */
558*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, PMBUS_VOUT_MAX);
559*4882a593Smuzhiyun if (ret < 0)
560*4882a593Smuzhiyun return ret;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun data->vout_max[page] = mp2975_vid2direct(info->vrm_version[page], ret &
563*4882a593Smuzhiyun GENMASK(8, 0));
564*4882a593Smuzhiyun return 0;
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun static int
mp2975_identify_vout_format(struct i2c_client * client,struct mp2975_data * data,int page)568*4882a593Smuzhiyun mp2975_identify_vout_format(struct i2c_client *client,
569*4882a593Smuzhiyun struct mp2975_data *data, int page)
570*4882a593Smuzhiyun {
571*4882a593Smuzhiyun int ret;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, MP2975_MFR_DC_LOOP_CTRL);
574*4882a593Smuzhiyun if (ret < 0)
575*4882a593Smuzhiyun return ret;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun if (ret & MP2975_VOUT_FORMAT)
578*4882a593Smuzhiyun data->vout_format[page] = vid;
579*4882a593Smuzhiyun else
580*4882a593Smuzhiyun data->vout_format[page] = direct;
581*4882a593Smuzhiyun return 0;
582*4882a593Smuzhiyun }
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun static int
mp2975_vout_ov_scale_get(struct i2c_client * client,struct mp2975_data * data,struct pmbus_driver_info * info)585*4882a593Smuzhiyun mp2975_vout_ov_scale_get(struct i2c_client *client, struct mp2975_data *data,
586*4882a593Smuzhiyun struct pmbus_driver_info *info)
587*4882a593Smuzhiyun {
588*4882a593Smuzhiyun int thres_dev, sense_ampl, ret;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 0);
591*4882a593Smuzhiyun if (ret < 0)
592*4882a593Smuzhiyun return ret;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /*
595*4882a593Smuzhiyun * Get divider for over- and under-voltage protection thresholds
596*4882a593Smuzhiyun * configuration from the Advanced Options of Auto Phase Shedding and
597*4882a593Smuzhiyun * decay register.
598*4882a593Smuzhiyun */
599*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, MP2975_MFR_APS_DECAY_ADV);
600*4882a593Smuzhiyun if (ret < 0)
601*4882a593Smuzhiyun return ret;
602*4882a593Smuzhiyun thres_dev = ret & MP2975_PRT_THRES_DIV_OV_EN ? MP2975_PROT_DEV_OV_ON :
603*4882a593Smuzhiyun MP2975_PROT_DEV_OV_OFF;
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun /* Select the gain of remote sense amplifier. */
606*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, PMBUS_VOUT_SCALE_LOOP);
607*4882a593Smuzhiyun if (ret < 0)
608*4882a593Smuzhiyun return ret;
609*4882a593Smuzhiyun sense_ampl = ret & MP2975_SENSE_AMPL ? MP2975_SENSE_AMPL_HALF :
610*4882a593Smuzhiyun MP2975_SENSE_AMPL_UNIT;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun data->vout_scale = sense_ampl * thres_dev;
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun return 0;
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun static int
mp2975_vout_per_rail_config_get(struct i2c_client * client,struct mp2975_data * data,struct pmbus_driver_info * info)618*4882a593Smuzhiyun mp2975_vout_per_rail_config_get(struct i2c_client *client,
619*4882a593Smuzhiyun struct mp2975_data *data,
620*4882a593Smuzhiyun struct pmbus_driver_info *info)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun int i, ret;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun for (i = 0; i < data->info.pages; i++) {
625*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, i);
626*4882a593Smuzhiyun if (ret < 0)
627*4882a593Smuzhiyun return ret;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun /* Obtain voltage reference offsets. */
630*4882a593Smuzhiyun ret = mp2975_vref_offset_get(client, data, i);
631*4882a593Smuzhiyun if (ret < 0)
632*4882a593Smuzhiyun return ret;
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun /* Obtain maximum voltage values. */
635*4882a593Smuzhiyun ret = mp2975_vout_max_get(client, data, info, i);
636*4882a593Smuzhiyun if (ret < 0)
637*4882a593Smuzhiyun return ret;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun /*
640*4882a593Smuzhiyun * Get VOUT format for READ_VOUT command : VID or direct.
641*4882a593Smuzhiyun * Pages on same device can be configured with different
642*4882a593Smuzhiyun * formats.
643*4882a593Smuzhiyun */
644*4882a593Smuzhiyun ret = mp2975_identify_vout_format(client, data, i);
645*4882a593Smuzhiyun if (ret < 0)
646*4882a593Smuzhiyun return ret;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun /*
649*4882a593Smuzhiyun * Set over-voltage fixed value. Thresholds are provided as
650*4882a593Smuzhiyun * fixed value, and tracking value. The minimum of them are
651*4882a593Smuzhiyun * exposed as over-voltage critical threshold.
652*4882a593Smuzhiyun */
653*4882a593Smuzhiyun data->vout_ov_fixed[i] = data->vref[i] +
654*4882a593Smuzhiyun DIV_ROUND_CLOSEST(data->vref_off[i] *
655*4882a593Smuzhiyun data->vout_scale,
656*4882a593Smuzhiyun 10);
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun return 0;
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun static struct pmbus_driver_info mp2975_info = {
663*4882a593Smuzhiyun .pages = 1,
664*4882a593Smuzhiyun .format[PSC_VOLTAGE_IN] = linear,
665*4882a593Smuzhiyun .format[PSC_VOLTAGE_OUT] = direct,
666*4882a593Smuzhiyun .format[PSC_TEMPERATURE] = direct,
667*4882a593Smuzhiyun .format[PSC_CURRENT_IN] = linear,
668*4882a593Smuzhiyun .format[PSC_CURRENT_OUT] = direct,
669*4882a593Smuzhiyun .format[PSC_POWER] = direct,
670*4882a593Smuzhiyun .m[PSC_TEMPERATURE] = 1,
671*4882a593Smuzhiyun .m[PSC_VOLTAGE_OUT] = 1,
672*4882a593Smuzhiyun .R[PSC_VOLTAGE_OUT] = 3,
673*4882a593Smuzhiyun .m[PSC_CURRENT_OUT] = 1,
674*4882a593Smuzhiyun .m[PSC_POWER] = 1,
675*4882a593Smuzhiyun .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT |
676*4882a593Smuzhiyun PMBUS_HAVE_IIN | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT |
677*4882a593Smuzhiyun PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP | PMBUS_HAVE_POUT |
678*4882a593Smuzhiyun PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT | PMBUS_PHASE_VIRTUAL,
679*4882a593Smuzhiyun .read_byte_data = mp2975_read_byte_data,
680*4882a593Smuzhiyun .read_word_data = mp2975_read_word_data,
681*4882a593Smuzhiyun };
682*4882a593Smuzhiyun
mp2975_probe(struct i2c_client * client)683*4882a593Smuzhiyun static int mp2975_probe(struct i2c_client *client)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun struct pmbus_driver_info *info;
686*4882a593Smuzhiyun struct mp2975_data *data;
687*4882a593Smuzhiyun int ret;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun data = devm_kzalloc(&client->dev, sizeof(struct mp2975_data),
690*4882a593Smuzhiyun GFP_KERNEL);
691*4882a593Smuzhiyun if (!data)
692*4882a593Smuzhiyun return -ENOMEM;
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun memcpy(&data->info, &mp2975_info, sizeof(*info));
695*4882a593Smuzhiyun info = &data->info;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun /* Identify multiphase configuration for rail 2. */
698*4882a593Smuzhiyun ret = mp2975_identify_multiphase_rail2(client);
699*4882a593Smuzhiyun if (ret < 0)
700*4882a593Smuzhiyun return ret;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun if (ret) {
703*4882a593Smuzhiyun /* Two rails are connected. */
704*4882a593Smuzhiyun data->info.pages = MP2975_PAGE_NUM;
705*4882a593Smuzhiyun data->info.phases[1] = ret;
706*4882a593Smuzhiyun data->info.func[1] = MP2975_RAIL2_FUNC;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun /* Identify multiphase configuration. */
710*4882a593Smuzhiyun ret = mp2975_identify_multiphase(client, data, info);
711*4882a593Smuzhiyun if (ret)
712*4882a593Smuzhiyun return ret;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun /* Identify VID setting per rail. */
715*4882a593Smuzhiyun ret = mp2975_identify_rails_vid(client, data, info);
716*4882a593Smuzhiyun if (ret < 0)
717*4882a593Smuzhiyun return ret;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun /* Obtain current sense gain of power stage. */
720*4882a593Smuzhiyun ret = mp2975_current_sense_gain_get(client, data);
721*4882a593Smuzhiyun if (ret)
722*4882a593Smuzhiyun return ret;
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun /* Obtain voltage reference values. */
725*4882a593Smuzhiyun ret = mp2975_vref_get(client, data, info);
726*4882a593Smuzhiyun if (ret)
727*4882a593Smuzhiyun return ret;
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun /* Obtain vout over-voltage scales. */
730*4882a593Smuzhiyun ret = mp2975_vout_ov_scale_get(client, data, info);
731*4882a593Smuzhiyun if (ret < 0)
732*4882a593Smuzhiyun return ret;
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun /* Obtain offsets, maximum and format for vout. */
735*4882a593Smuzhiyun ret = mp2975_vout_per_rail_config_get(client, data, info);
736*4882a593Smuzhiyun if (ret)
737*4882a593Smuzhiyun return ret;
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun return pmbus_do_probe(client, info);
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun static const struct i2c_device_id mp2975_id[] = {
743*4882a593Smuzhiyun {"mp2975", 0},
744*4882a593Smuzhiyun {}
745*4882a593Smuzhiyun };
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mp2975_id);
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun static const struct of_device_id __maybe_unused mp2975_of_match[] = {
750*4882a593Smuzhiyun {.compatible = "mps,mp2975"},
751*4882a593Smuzhiyun {}
752*4882a593Smuzhiyun };
753*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mp2975_of_match);
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun static struct i2c_driver mp2975_driver = {
756*4882a593Smuzhiyun .driver = {
757*4882a593Smuzhiyun .name = "mp2975",
758*4882a593Smuzhiyun .of_match_table = of_match_ptr(mp2975_of_match),
759*4882a593Smuzhiyun },
760*4882a593Smuzhiyun .probe_new = mp2975_probe,
761*4882a593Smuzhiyun .remove = pmbus_do_remove,
762*4882a593Smuzhiyun .id_table = mp2975_id,
763*4882a593Smuzhiyun };
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun module_i2c_driver(mp2975_driver);
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun MODULE_AUTHOR("Vadim Pasternak <vadimp@nvidia.com>");
768*4882a593Smuzhiyun MODULE_DESCRIPTION("PMBus driver for MPS MP2975 device");
769*4882a593Smuzhiyun MODULE_LICENSE("GPL");
770