77 	 * Set the drive phase offset based on speed mode to achieve hold times.  in dw_mci_rk3288_set_ios()
103 		int phase;  in dw_mci_rk3288_set_ios()  local
106 		 * In almost all cases a 90 degree phase offset will provide  in dw_mci_rk3288_set_ios()
111 		phase = 90;  in dw_mci_rk3288_set_ios()
117 			 * bus width is 8 we need to double the phase offset  in dw_mci_rk3288_set_ios()
121 				phase = 180;  in dw_mci_rk3288_set_ios()
133 			phase = 180;  in dw_mci_rk3288_set_ios()
137 		clk_set_phase(priv->drv_clk, phase);  in dw_mci_rk3288_set_ios()
165 	 * one phase from degree list and loop around until we get one.  in dw_mci_v2_execute_tuning()
166 	 * It's impossible all 4 fixed phase won't be able to work.  in dw_mci_v2_execute_tuning()
175                         * Tuning error, the phase is a bad phase,  in dw_mci_v2_execute_tuning()
176                         * then try using the calculated best phase.  in dw_mci_v2_execute_tuning()
178 …                   dev_info(host->dev, "V2 tuned phase to %d error, try the best phase\n", degree);  in dw_mci_v2_execute_tuning()
193 	dev_info(host->dev, "Successfully tuned phase to %d\n", degree);  in dw_mci_v2_execute_tuning()
233 	/* Try each phase and extract good ranges */  in dw_mci_rk3288_execute_tuning()
286 		dev_info(host->dev, "All phases work, using default phase %d.",  in dw_mci_rk3288_execute_tuning()
303 		dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",  in dw_mci_rk3288_execute_tuning()
312 	dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",  in dw_mci_rk3288_execute_tuning()
328 	 * using any middle phase located between 270 and 360.  in dw_mci_rk3288_execute_tuning()
332 	 * bad phases exceed 180, the middle phase of rollback  in dw_mci_rk3288_execute_tuning()
342 	dev_info(host->dev, "Successfully tuned phase to %d\n",  in dw_mci_rk3288_execute_tuning()
376 	if (of_property_read_u32(np, "rockchip,default-sample-phase",  in dw_mci_rk3288_parse_dt()