| /OK3568_Linux_fs/kernel/drivers/mtd/nand/ |
| H A D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/ |
| H A D | mtk-nand.txt | 1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
5 the nand controller interface driver and the ECC engine driver.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
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| H A D | nand-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
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| H A D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
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| H A D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding
5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
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| H A D | rockchip,nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoCs NAND FLASH Controller (NFC)
10 - $ref: "nand-controller.yaml#"
13 - Heiko Stuebner <heiko@sntech.de>
18 - const: rockchip,px30-nfc
19 - const: rockchip,rk2928-nfc
20 - const: rockchip,rv1108-nfc
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| H A D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
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| H A D | denali,nand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Denali NAND controller
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
19 reg-names:
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| H A D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
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| H A D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
19 the core NAND controller, of the following form:
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
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| H A D | qcom_nandc.txt | 1 * Qualcomm NAND controller
4 - compatible: must be one of the following:
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
12 - reg: MMIO address range
13 - clocks: must contain core clock and always on clock
14 - clock-names: must contain "core" for the core clock and "aon" for the
18 - dmas: DMA specifier, consisting of a phandle to the ADM DMA
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
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| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ |
| H A D | tegra_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
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| H A D | sunxi_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
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| H A D | mtk_nand.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * MTK NAND Flash controller driver.
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
22 /* NAND controller register definition */
90 #define MTK_NAME "mtk-nand"
127 struct nand_chip nand; member
147 struct mtk_ecc *ecc; member
179 static inline struct mtk_nfc_nand_chip *to_mtk_nand(struct nand_chip *nand) in to_mtk_nand() argument
181 return container_of(nand, struct mtk_nfc_nand_chip, nand); in to_mtk_nand()
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| H A D | meson_nand.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Amlogic Meson Nand Flash Controller Driver
10 #include <linux/dma-mapping.h>
76 #define ECC_CHECK_RETURN_FF (-1)
91 /* nand flash controller delay 3 ns */
109 struct nand_chip nand; member
126 u32 strength; member
188 #define MESON_ECC_DATA(b, s) { .bch = (b), .strength = (s)}
199 static int meson_nand_calc_ecc_bytes(int step_size, int strength) in meson_nand_calc_ecc_bytes() argument
203 if (step_size == 512 && strength == 8) in meson_nand_calc_ecc_bytes()
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| H A D | nand_base.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
37 #include <linux/mtd/nand.h>
52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
59 info->group = 0; in nand_pairing_dist3_get_info()
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| H A D | arasan-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
137 * @node: Used to store NAND chips into a list
138 * @chip: NAND chip information structure
140 * @rb: Ready-busy line
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| H A D | stm32_fmc2_nand.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
26 /* ECC step size */
35 /* Max requests done for a 8k nand page size */
41 /* Max ECC buffer length */
246 struct stm32_fmc2_nand nand; member
281 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); in stm32_fmc2_nfc_timings_init()
282 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); in stm32_fmc2_nfc_timings_init() local
283 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_nfc_timings_init()
287 regmap_update_bits(nfc->regmap, FMC2_PCR, in stm32_fmc2_nfc_timings_init()
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| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ingenic/ |
| H A D | ingenic_nand_drv.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ47xx NAND driver
24 #include <linux/jz4780-nemc.h>
28 #define DRV_NAME "ingenic-nand"
44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
78 return -ERANGE; in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc()
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| /OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 2 menuconfig NAND config
3 bool "Raw NAND Device Support"
4 if NAND
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
19 bool "Support Atmel NAND controller"
22 Enable this driver for NAND flash platforms using an Atmel NAND
28 bool "Atmel Hardware ECC"
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| H A D | stm32_fmc2_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
10 #include <nand.h>
18 /* ECC step size */
161 struct stm32_fmc2_nand nand; member
181 struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller); in stm32_fmc2_timings_init()
182 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); in stm32_fmc2_timings_init() local
183 struct stm32_fmc2_timings *timings = &nand->timings; in stm32_fmc2_timings_init()
184 u32 pcr = readl(fmc2->io_base + FMC2_PCR); in stm32_fmc2_timings_init()
189 pcr |= FMC2_PCR_TCLR(timings->tclr); in stm32_fmc2_timings_init()
191 pcr |= FMC2_PCR_TAR(timings->tar); in stm32_fmc2_timings_init()
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| H A D | rockchip_nand_v9.c | 2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <nand.h>
17 #include <linux/mtd/nand.h>
113 writel(0, rknand->regs + NANDC_REG_V9_RANDMZ); in rockchip_nand_init()
114 writel(0, rknand->regs + NANDC_REG_V9_DMA_CFG); in rockchip_nand_init()
115 writel(0, rknand->regs + NANDC_REG_V9_BCHCTL); in rockchip_nand_init()
116 writel(NANDC_V9_FM_WP, rknand->regs + NANDC_REG_V9_FMCTL); in rockchip_nand_init()
117 writel(0x1081, rknand->regs + NANDC_REG_V9_FMWAIT); in rockchip_nand_init()
123 struct rk_nand *rknand = to_rknand(chip->controller); in rockchip_nand_select_chip()
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| H A D | rockchip_nand.c | 2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <nand.h>
107 writel(0, rknand->regs + NANDC_REG_V6_RANDMZ); in rockchip_nand_init()
108 writel(0, rknand->regs + NANDC_REG_V6_DMA_CFG); in rockchip_nand_init()
109 writel(0, rknand->regs + NANDC_REG_V6_BCHCTL); in rockchip_nand_init()
110 writel(NANDC_V6_FM_WP, rknand->regs + NANDC_REG_V6_FMCTL); in rockchip_nand_init()
111 writel(0x1081, rknand->regs + NANDC_REG_V6_FMWAIT); in rockchip_nand_init()
117 struct rk_nand *rknand = to_rknand(chip->controller); in rockchip_nand_select_chip()
122 reg = readl(rknand->regs + NANDC_REG_V6_FMCTL); in rockchip_nand_select_chip()
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| H A D | fsmc_nand.c | 8 * SPDX-License-Identifier: GPL-2.0+
12 #include <nand.h>
25 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
62 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
63 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
98 * ECC placement definitions in oobfree type format
99 * There are 13 bytes of ecc for every 512 byte block and it has to be read
102 * Managing the ecc bytes in the following way makes it easier for software to
103 * read ecc bytes consecutive to data bytes. This way is similar to
104 * oobfree structure maintained already in u-boot nand driver
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| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/atmel/ |
| H A D | pmecc.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
26 * Add Programmable Multibit ECC support for various AT91 SoC
29 * Add Nand Flash Controller support for SAMA5 SoC
33 * ECC algorithm is left to the software. The hardware/software repartition
37 * sub-section.
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