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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Multi Core Timer (MCT)
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dexynos4210.dtsi2 * Samsung's Exynos4210 SoC device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2010-2011 Linaro Ltd.
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
23 #include "exynos4210-pinctrl.dtsi"
24 #include "exynos4210-pinctrl-uboot.dtsi"
27 compatible = "samsung,exynos4210";
35 pd_lcd1: lcd1-power-domain@10023CA0 {
36 compatible = "samsung,exynos4210-pd";
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H A Dexynos4x12.dtsi21 #include "exynos4x12-pinctrl.dtsi"
22 #include "exynos4x12-pinctrl-uboot.dtsi"
32 pd_isp: isp-power-domain@10023CA0 {
33 compatible = "samsung,exynos4210-pd";
37 clock: clock-controller@10030000 {
38 compatible = "samsung,exynos4412-clock";
40 #clock-cells = <1>;
43 mct@10050000 {
44 compatible = "samsung,exynos4412-mct";
46 interrupt-parent = <&mct_map>;
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC device tree source
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
20 #include "exynos4-cpu-thermal.dtsi"
23 compatible = "samsung,exynos4210", "samsung,exynos4";
32 #address-cells = <1>;
33 #size-cells = <0>;
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H A Dexynos54xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
28 arm_a7_pmu: arm-a7-pmu {
29 compatible = "arm,cortex-a7-pmu";
30 interrupt-parent = <&gic>;
38 arm_a15_pmu: arm-a15-pmu {
39 compatible = "arm,cortex-a15-pmu";
40 interrupt-parent = <&combiner>;
49 compatible = "arm,armv7-timer";
54 clock-frequency = <24000000>;
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H A Dexynos5260.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos5260-clk.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
39 compatible = "arm,cortex-a15";
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H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
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H A Dexynos5250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include <dt-bindings/clock/exynos5250.h>
19 #include "exynos4-cpu-thermal.dtsi"
20 #include <dt-bindings/clock/exynos-audss-clk.h>
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a15";
58 clock-names = "cpu";
59 operating-points-v2 = <&cpu0_opp_table>;
60 #cooling-cells = <2>; /* min followed by max */
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H A Dexynos4412.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a9";
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
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H A Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Universal C210 board device tree source
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
9 * Samsung's Exynos4210 rev0 SoC.
12 /dts-v1/;
13 #include "exynos4210.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
17 model = "Samsung Universal C210 based on Exynos4210 rev0";
18 compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4";
28 stdout-path = "serial2:115200n8";
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H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
46 compatible = "operating-points-v2";
47 opp-shared;
49 opp-1800000000 {
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000 1250000 1500000>;
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H A Dexynos5410.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
42 compatible = "arm,cortex-a15";
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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dexynos_mct.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/arch/arm/mach-exynos4/mct.c
7 * Exynos4 MCT(Multi-Core Timer) support
147 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); in exynos4_mct_write()
161 * exynos4_read_count_64 - Read all 64-bits of the global counter
163 * This will read all 64-bits of the global counter taking care to make sure
164 * that the upper and lower half match. Note that reading the MCT can be quite
165 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
185 * exynos4_read_count_32 - Read the lower 32-bits of the global counter
187 * This will read just the lower 32-bits of the global counter. This is marked
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/OK3568_Linux_fs/kernel/drivers/clk/samsung/
H A Dclk-exynos4.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <dt-bindings/clock/exynos4.h>
13 #include <linux/clk-provider.h>
19 #include "clk-cpu.h"
140 EXYNOS4210, enumerator
295 /* Exynos 4210-specific parent groups */
334 /* Exynos 4x12-specific parent groups */
438 /* list of mux clocks supported in exynos4210 soc */
678 /* list of divider clocks supported in exynos4210 soc */
874 GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/
H A Dexynos5433.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/exynos5433.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
24 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a53-pmu";
32 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
36 compatible = "arm,cortex-a57-pmu";
41 interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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