xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Samsung Exynos SoC Multi Core Timer (MCT)
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Krzysztof Kozlowski <krzk@kernel.org>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |+
13*4882a593Smuzhiyun  The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14*4882a593Smuzhiyun  global timer and CPU local timers. The global timer is a 64-bit free running
15*4882a593Smuzhiyun  up-counter and can generate 4 interrupts when the counter reaches one of the
16*4882a593Smuzhiyun  four preset counter values. The CPU local timers are 32-bit free running
17*4882a593Smuzhiyun  down-counters and generate an interrupt when the counter expires. There is
18*4882a593Smuzhiyun  one CPU local timer instantiated in MCT for every CPU in the system.
19*4882a593Smuzhiyun
20*4882a593Smuzhiyunproperties:
21*4882a593Smuzhiyun  compatible:
22*4882a593Smuzhiyun    enum:
23*4882a593Smuzhiyun      - samsung,exynos4210-mct
24*4882a593Smuzhiyun      - samsung,exynos4412-mct
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  clocks:
27*4882a593Smuzhiyun    minItems: 2
28*4882a593Smuzhiyun    maxItems: 2
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun  clock-names:
31*4882a593Smuzhiyun    items:
32*4882a593Smuzhiyun      - pattern: "^(fin_pll|mct)$"
33*4882a593Smuzhiyun      - pattern: "^(fin_pll|mct)$"
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  reg:
36*4882a593Smuzhiyun    maxItems: 1
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun  interrupts:
39*4882a593Smuzhiyun    description: |
40*4882a593Smuzhiyun      Interrupts should be put in specific order. This is, the local timer
41*4882a593Smuzhiyun      interrupts should be specified after the four global timer interrupts
42*4882a593Smuzhiyun      have been specified:
43*4882a593Smuzhiyun      0: Global Timer Interrupt 0
44*4882a593Smuzhiyun      1: Global Timer Interrupt 1
45*4882a593Smuzhiyun      2: Global Timer Interrupt 2
46*4882a593Smuzhiyun      3: Global Timer Interrupt 3
47*4882a593Smuzhiyun      4: Local Timer Interrupt 0
48*4882a593Smuzhiyun      5: Local Timer Interrupt 1
49*4882a593Smuzhiyun      6: ..
50*4882a593Smuzhiyun      7: ..
51*4882a593Smuzhiyun      i: Local Timer Interrupt n
52*4882a593Smuzhiyun      For MCT block that uses a per-processor interrupt for local timers, such
53*4882a593Smuzhiyun      as ones compatible with "samsung,exynos4412-mct", only one local timer
54*4882a593Smuzhiyun      interrupt might be specified, meaning that all local timers use the same
55*4882a593Smuzhiyun      per processor interrupt.
56*4882a593Smuzhiyun    minItems: 5               # 4 Global + 1 local
57*4882a593Smuzhiyun    maxItems: 20              # 4 Global + 16 local
58*4882a593Smuzhiyun
59*4882a593Smuzhiyunrequired:
60*4882a593Smuzhiyun  - compatible
61*4882a593Smuzhiyun  - clock-names
62*4882a593Smuzhiyun  - clocks
63*4882a593Smuzhiyun  - interrupts
64*4882a593Smuzhiyun  - reg
65*4882a593Smuzhiyun
66*4882a593SmuzhiyunadditionalProperties: false
67*4882a593Smuzhiyun
68*4882a593Smuzhiyunexamples:
69*4882a593Smuzhiyun  - |
70*4882a593Smuzhiyun    // In this example, the IP contains two local timers, using separate
71*4882a593Smuzhiyun    // interrupts, so two local timer interrupts have been specified,
72*4882a593Smuzhiyun    // in addition to four global timer interrupts.
73*4882a593Smuzhiyun    #include <dt-bindings/clock/exynos4.h>
74*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun    timer@10050000 {
77*4882a593Smuzhiyun        compatible = "samsung,exynos4210-mct";
78*4882a593Smuzhiyun        reg = <0x10050000 0x800>;
79*4882a593Smuzhiyun        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
80*4882a593Smuzhiyun        clock-names = "fin_pll", "mct";
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
83*4882a593Smuzhiyun                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
84*4882a593Smuzhiyun                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
85*4882a593Smuzhiyun                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
86*4882a593Smuzhiyun                     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
87*4882a593Smuzhiyun                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
88*4882a593Smuzhiyun    };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun  - |
91*4882a593Smuzhiyun    // In this example, the timer interrupts are connected to two separate
92*4882a593Smuzhiyun    // interrupt controllers. Hence, an interrupts-extended is needed.
93*4882a593Smuzhiyun    #include <dt-bindings/clock/exynos4.h>
94*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun    timer@101c0000 {
97*4882a593Smuzhiyun        compatible = "samsung,exynos4210-mct";
98*4882a593Smuzhiyun        reg = <0x101C0000 0x800>;
99*4882a593Smuzhiyun        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
100*4882a593Smuzhiyun        clock-names = "fin_pll", "mct";
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun        interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
103*4882a593Smuzhiyun                              <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
104*4882a593Smuzhiyun                              <&combiner 12 6>,
105*4882a593Smuzhiyun                              <&combiner 12 7>,
106*4882a593Smuzhiyun                              <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
107*4882a593Smuzhiyun                              <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
108*4882a593Smuzhiyun    };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun  - |
111*4882a593Smuzhiyun    // In this example, the IP contains four local timers, but using
112*4882a593Smuzhiyun    // a per-processor interrupt to handle them. Only one first local
113*4882a593Smuzhiyun    // interrupt is specified.
114*4882a593Smuzhiyun    #include <dt-bindings/clock/exynos4.h>
115*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun    timer@10050000 {
118*4882a593Smuzhiyun        compatible = "samsung,exynos4412-mct";
119*4882a593Smuzhiyun        reg = <0x10050000 0x800>;
120*4882a593Smuzhiyun        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
121*4882a593Smuzhiyun        clock-names = "fin_pll", "mct";
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
124*4882a593Smuzhiyun                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
125*4882a593Smuzhiyun                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
126*4882a593Smuzhiyun                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
127*4882a593Smuzhiyun                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
128*4882a593Smuzhiyun    };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun  - |
131*4882a593Smuzhiyun    // In this example, the IP contains four local timers, but using
132*4882a593Smuzhiyun    // a per-processor interrupt to handle them. All the local timer
133*4882a593Smuzhiyun    // interrupts are specified.
134*4882a593Smuzhiyun    #include <dt-bindings/clock/exynos4.h>
135*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun    timer@10050000 {
138*4882a593Smuzhiyun        compatible = "samsung,exynos4412-mct";
139*4882a593Smuzhiyun        reg = <0x10050000 0x800>;
140*4882a593Smuzhiyun        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
141*4882a593Smuzhiyun        clock-names = "fin_pll", "mct";
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
144*4882a593Smuzhiyun                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
145*4882a593Smuzhiyun                     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
146*4882a593Smuzhiyun                     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
147*4882a593Smuzhiyun                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
148*4882a593Smuzhiyun                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
149*4882a593Smuzhiyun                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>,
150*4882a593Smuzhiyun                     <GIC_PPI 42 IRQ_TYPE_LEVEL_HIGH>;
151*4882a593Smuzhiyun    };
152