1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Samsung's Exynos4x12 SoCs device tree source 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5*4882a593Smuzhiyun * http://www.samsung.com 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 8*4882a593Smuzhiyun * based board files can include this file and provide values for board specfic 9*4882a593Smuzhiyun * bindings. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Note: This file does not include device nodes for all the controllers in 12*4882a593Smuzhiyun * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional 13*4882a593Smuzhiyun * nodes can be added to this file. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 16*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 17*4882a593Smuzhiyun` * published by the Free Software Foundation. 18*4882a593Smuzhiyun*/ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun#include "exynos4.dtsi" 21*4882a593Smuzhiyun#include "exynos4x12-pinctrl.dtsi" 22*4882a593Smuzhiyun#include "exynos4x12-pinctrl-uboot.dtsi" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun/ { 25*4882a593Smuzhiyun aliases { 26*4882a593Smuzhiyun pinctrl0 = &pinctrl_0; 27*4882a593Smuzhiyun pinctrl1 = &pinctrl_1; 28*4882a593Smuzhiyun pinctrl2 = &pinctrl_2; 29*4882a593Smuzhiyun pinctrl3 = &pinctrl_3; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun pd_isp: isp-power-domain@10023CA0 { 33*4882a593Smuzhiyun compatible = "samsung,exynos4210-pd"; 34*4882a593Smuzhiyun reg = <0x10023CA0 0x20>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun clock: clock-controller@10030000 { 38*4882a593Smuzhiyun compatible = "samsung,exynos4412-clock"; 39*4882a593Smuzhiyun reg = <0x10030000 0x20000>; 40*4882a593Smuzhiyun #clock-cells = <1>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun mct@10050000 { 44*4882a593Smuzhiyun compatible = "samsung,exynos4412-mct"; 45*4882a593Smuzhiyun reg = <0x10050000 0x800>; 46*4882a593Smuzhiyun interrupt-parent = <&mct_map>; 47*4882a593Smuzhiyun interrupts = <0>, <1>, <2>, <3>, <4>; 48*4882a593Smuzhiyun clocks = <&clock 3>, <&clock 344>; 49*4882a593Smuzhiyun clock-names = "fin_pll", "mct"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun mct_map: mct-map { 52*4882a593Smuzhiyun #interrupt-cells = <1>; 53*4882a593Smuzhiyun #address-cells = <0>; 54*4882a593Smuzhiyun #size-cells = <0>; 55*4882a593Smuzhiyun interrupt-map = <0 &gic 0 57 0>, 56*4882a593Smuzhiyun <1 &combiner 12 5>, 57*4882a593Smuzhiyun <2 &combiner 12 6>, 58*4882a593Smuzhiyun <3 &combiner 12 7>, 59*4882a593Smuzhiyun <4 &gic 1 12 0>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun pinctrl_0: pinctrl@11400000 { 64*4882a593Smuzhiyun compatible = "samsung,exynos4x12-pinctrl"; 65*4882a593Smuzhiyun reg = <0x11400000 0x1000>; 66*4882a593Smuzhiyun interrupts = <0 47 0>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun pinctrl_1: pinctrl@11000000 { 70*4882a593Smuzhiyun compatible = "samsung,exynos4x12-pinctrl"; 71*4882a593Smuzhiyun reg = <0x11000000 0x1000>; 72*4882a593Smuzhiyun interrupts = <0 46 0>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun wakup_eint: wakeup-interrupt-controller { 75*4882a593Smuzhiyun compatible = "samsung,exynos4210-wakeup-eint"; 76*4882a593Smuzhiyun interrupt-parent = <&gic>; 77*4882a593Smuzhiyun interrupts = <0 32 0>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun pinctrl_2: pinctrl@03860000 { 82*4882a593Smuzhiyun compatible = "samsung,exynos4x12-pinctrl"; 83*4882a593Smuzhiyun reg = <0x03860000 0x1000>; 84*4882a593Smuzhiyun interrupt-parent = <&combiner>; 85*4882a593Smuzhiyun interrupts = <10 0>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun pinctrl_3: pinctrl@106E0000 { 89*4882a593Smuzhiyun compatible = "samsung,exynos4x12-pinctrl"; 90*4882a593Smuzhiyun reg = <0x106E0000 0x1000>; 91*4882a593Smuzhiyun interrupts = <0 72 0>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun g2d@10800000 { 95*4882a593Smuzhiyun compatible = "samsung,exynos4212-g2d"; 96*4882a593Smuzhiyun reg = <0x10800000 0x1000>; 97*4882a593Smuzhiyun interrupts = <0 89 0>; 98*4882a593Smuzhiyun clocks = <&clock 177>, <&clock 277>; 99*4882a593Smuzhiyun clock-names = "sclk_fimg2d", "fimg2d"; 100*4882a593Smuzhiyun status = "disabled"; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun}; 103