| /OK3568_Linux_fs/kernel/drivers/mtd/nand/ |
| H A D | ecc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic Error-Correcting Code (ECC) engine
10 * This file describes the abstraction of any NAND ECC engine. It has been
11 * designed to fit most cases, including parallel NANDs and SPI-NANDs.
13 * There are three main situations where instantiating this ECC engine makes
15 * - external: The ECC engine is outside the NAND pipeline, typically this
16 * is a software ECC engine, or an hardware engine that is
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
20 * controllers. In the pipeline case, the ECC bytes are
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/ |
| H A D | nand-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
31 pattern: "^nand-controller(@.*)?"
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| H A D | mtk-nand.txt | 5 the nand controller interface driver and the ECC engine driver.
15 - compatible: Should be one of
16 "mediatek,mt2701-nfc",
17 "mediatek,mt2712-nfc",
18 "mediatek,mt7622-nfc".
19 - reg: Base physical address and size of NFI.
20 - interrupts: Interrupts of NFI.
21 - clocks: NFI required clocks.
22 - clock-names: NFI clocks internal name.
23 - ecc-engine: Required ECC Engine node.
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| H A D | atmel-nand.txt | 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
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| H A D | gpmc-nand.txt | 7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
10 For NAND specific properties such as ECC modes or bus width, please refer to
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
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| H A D | ingenic,nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
18 - ingenic,jz4740-nand
19 - ingenic,jz4725b-nand
20 - ingenic,jz4780-nand
24 - description: Bank number, offset and size of first attached NAND chip
25 - description: Bank number, offset and size of second attached NAND chip
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| H A D | brcm,brcmnand.txt | 3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
4 flash chips. It has a memory-mapped register interface for both control
6 paired with a custom DMA engine (inventively named "Flash DMA") which supports
15 - compatible : May contain an SoC-specific compatibility string (see below)
16 to account for any SoC-specific hardware bits that may be
21 string, like "brcm,brcmnand-v7.0"
23 brcm,brcmnand-v2.1
24 brcm,brcmnand-v2.2
25 brcm,brcmnand-v4.0
26 brcm,brcmnand-v5.0
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| /OK3568_Linux_fs/u-boot/doc/ |
| H A D | README.nand | 8 # SPDX-License-Identifier: GPL-2.0+
32 If `clean' is specified, a JFFS2-style clean marker is written to
49 Read `size' bytes from the out-of-band data area corresponding to
51 data for one 512-byte page or 2 256-byte pages. There is no check
52 for bad blocks or ECC errors.
68 described above -- with the additional check that all pages at the end
73 [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
76 Write `size' bytes from `addr' to the out-of-band data area
78 of data for one 512-byte page or 2 256-byte pages. There is no check
84 "addr" in memory. This is a raw access, so ECC is avoided and the
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| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ingenic/ |
| H A D | ingenic_ecc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * JZ47xx ECC common code
18 * ingenic_ecc_calculate() - calculate ECC for a data buffer
19 * @ecc: ECC device.
20 * @params: ECC parameters.
22 * @ecc_code: output buffer with ECC.
24 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
27 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
31 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
35 * ingenic_ecc_correct() - detect and correct bit errors
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| /OK3568_Linux_fs/kernel/include/linux/mtd/ |
| H A D | nand.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
74 * These information are usually used by specific sub-layers to select the
86 * enum nand_page_io_req_type - Direction of an I/O request
96 * struct nand_page_io_req - NAND I/O request object
107 * This object is used to pass per-page I/O requests to NAND sub-layers. This
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| /OK3568_Linux_fs/kernel/include/linux/ |
| H A D | ccp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
26 * ccp_present - check if a CCP device is present
28 * Returns zero if a CCP device is present, -ENODEV otherwise.
33 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
38 * ccp_version - get the version of the CCP
45 * ccp_enqueue_cmd - queue an operation for processing by the CCP
54 * result in a return code of -EBUSY.
60 * will be -EINPROGRESS. Any other "err" value during callback is
64 * the return code is -EINPROGRESS or
65 * the return code is -EBUSY and CCP_CMD_MAY_BACKLOG flag is set
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| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ |
| H A D | omap2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
20 #include <linux/omap-dma.h>
29 #include <linux/omap-gpmc.h>
30 #include <linux/platform_data/mtd-nand-omap2.h>
32 #define DRIVER_NAME "omap2-nand"
122 /* GPMC ecc engine settings for read */
129 /* GPMC ecc engine settings for write */
170 /* fields specific for BCHx_HW ECC scheme */
182 * omap_prefetch_enable - configures and starts prefetch transfer
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| H A D | arasan-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
140 * @rb: Ready-busy line
144 * @ecc_conf: Hardware ECC configuration value
145 * @strength: Register value of the ECC strength
148 * @ecc_bits: Exact number of ECC bits per syndrome
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| H A D | cadence-nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
24 * - PIO - can work in master or slave DMA
25 * - CDMA - needs Master DMA for accessing command descriptors.
26 * - Generic mode - can use only slave DMA.
88 /* Command Engine threads state. */
91 /* Command Engine interrupt thread error status. */
93 /* Command Engine interrupt thread error enable. */
95 /* Command Engine interrupt thread complete status. */
115 /* Size of not-last data sector. */
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| /OK3568_Linux_fs/u-boot/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 9 This option, if enabled, provides more flexible and linux-like
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
28 bool "Atmel Hardware ECC"
32 bool "Atmel Programmable Multibit ECC (PMECC)"
36 The Programmable Multibit ECC (PMECC) controller is a programmable
40 int "PMECC Correctable ECC Bits"
44 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
59 Generate Programmable Multibit ECC (PMECC) header for SPL image.
113 of OOB area before last ECC sector data starts. This is potentially
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| H A D | tegra_nand.c | 7 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch-tegra/clk_rst.h>
30 /* ECC bytes to be generated for tag data */
35 .compatible = "nvidia,tegra20-nand",
42 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
44 * Main area Ecc(36)
46 * Tag data Ecc(4)
92 struct gpio_desc wp_gpio; /* write-protect GPIO */
113 * 1 - Command completed
114 * 0 - Timeout
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| H A D | omap_gpmc.c | 2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
55 * omap_nand_hwcontrol - Set the address pointers corretly for the
63 int cs = info->cs; in omap_nand_hwcontrol()
71 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; in omap_nand_hwcontrol()
74 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; in omap_nand_hwcontrol()
77 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; in omap_nand_hwcontrol()
82 writeb(cmd, this->IO_ADDR_W); in omap_nand_hwcontrol()
90 return gpmc_cfg->status & (1 << (8 + info->ws)); in omap_dev_ready()
94 * gen_true_ecc - This function will generate true ECC value, which
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| H A D | sunxi_nand_spl.c | 2 * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
3 * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
5 * SPDX-License-Identifier: GPL-2.0+
47 #define NFC_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
128 } while (--timeout_us); in check_value_inner()
150 return -ETIMEDOUT; in nand_wait_cmd_fifo_empty()
161 return -ETIMEDOUT; in nand_wait_int()
209 writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size), in nand_apply_config()
211 writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT); in nand_apply_config()
212 writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA); in nand_apply_config()
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1021atwr/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
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| /OK3568_Linux_fs/u-boot/include/ |
| H A D | fsl_fman.h | 4 * Copyright 2010-2011 Freescale Semiconductor, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
78 u32 fmbm_rfne; /* Rx frame next engine */
80 u32 fmbm_rfpne; /* Rx frame parser next engine */
90 u32 fmbm_rfene; /* Rx frame enqueue next engine */
120 /* FMBM_RCFG - Rx configuration */
125 /* FMBM_RST - Rx status */
128 /* FMBM_RFCA - Rx frame command attributes */
133 /* FMBM_RSTC - Rx statistics */
143 u32 fmbm_tfne; /* Tx frame next engine */
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| /OK3568_Linux_fs/u-boot/board/freescale/ls1021aqds/ |
| H A D | README | 2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
22 up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
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| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 11 ---------
12 The LS1043A integrated multicore processor combines four ARM Cortex-A53
18 - Four 64-bit ARM Cortex-A53 CPUs
19 - 1 MB unified L2 Cache
20 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
22 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
24 - Packet parsing, classification, and distribution (FMan)
25 - Queue management for scheduling, packet sequencing, and congestion
27 - Hardware buffer management for buffer allocation and de-allocation (BMan)
28 - Cryptography acceleration (SEC)
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| /OK3568_Linux_fs/kernel/drivers/crypto/ccp/ |
| H A D | ccp-ops.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2019 Advanced Micro Devices, Inc.
11 #include <linux/dma-mapping.h>
19 #include "ccp-dev.h"
56 #define CCP_NEW_JOBID(ccp) ((ccp->vdata->version == CCP_VERSION(3, 0)) ? \
61 return atomic_inc_return(&ccp->current_id) & CCP_JOBID_MASK; in ccp_gen_jobid()
66 if (wa->dma_count) in ccp_sg_free()
67 dma_unmap_sg(wa->dma_dev, wa->dma_sg_head, wa->nents, wa->dma_dir); in ccp_sg_free()
69 wa->dma_count = 0; in ccp_sg_free()
78 wa->sg = sg; in ccp_init_sg_workarea()
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| /OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/atmel/ |
| H A D | pmecc.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
26 * Add Programmable Multibit ECC support for various AT91 SoC
32 * The PMECC is an hardware assisted BCH engine, which means part of the
33 * ECC algorithm is left to the software. The hardware/software repartition
37 * sub-section.
41 * to expose the needed lib/bch.c helpers/functions and re-use them here.
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| /OK3568_Linux_fs/kernel/drivers/edac/ |
| H A D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
64 When this option is enabled, it will disable the hardware-driven
68 It should be noticed that keeping both GHES and a hardware-driven
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