u-boot/include/fsl_fman.h

4  * Copyright 2010-2011 Freescale Semiconductor, Inc.
6  * SPDX-License-Identifier:	GPL-2.0+
78 	u32 fmbm_rfne;	/* Rx frame next engine */
80 	u32 fmbm_rfpne;	/* Rx frame parser next engine */
90 	u32 fmbm_rfene;		/* Rx frame enqueue next engine */
120 /* FMBM_RCFG - Rx configuration */
125 /* FMBM_RST - Rx status */
128 /* FMBM_RFCA - Rx frame command attributes */
133 /* FMBM_RSTC - Rx statistics */
143 	u32 fmbm_tfne;	/* Tx frame next engine */
147 	u32 fmbm_tfene;	/* Tx frame enqueue next engine */
169 /* FMBM_TCFG - Tx configuration */
173 /* FMBM_TST - Tx status */
176 /* FMBM_TFCA - Tx frame command attributes */
181 /* FMBM_TSTC - Tx statistics counters */
184 /* FMBM_INIT - BMI initialization register */
187 /* FMBM_CFG1 - BMI configuration 1 */
192 /* FMBM_IEVR - interrupt event */
193 #define FMBM_IEVR_PEC		0x80000000 /* pipeline table ECC err detected */
194 #define FMBM_IEVR_LEC		0x40000000 /* linked list RAM ECC error */
195 #define FMBM_IEVR_SEC		0x20000000 /* statistics count RAM ECC error */
198 /* FMBM_IER - interrupt enable */
205 /* FMBM_PP - BMI Port Parameters */
207 #define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
209 #define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
211 /* FMBM_PFS - BMI Port FIFO Size */
215 /* FMQM_GC - global configuration */
224 /* FMQM_EIE - error interrupt event register */
225 #define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
229 /* FMQM_EIEN - error interrupt enable register */
230 #define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
234 /* FMQM_IE - interrupt event register */
235 #define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
238 /* FMQM_IEN - interrupt enable register */
239 #define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
242 /* NIA - next invoked action */
279 	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
283 /* FMDMSR - Fman DMA status register */
286 #define FMDMSR_RDB_ECC		0x04000000 /* read buffer ECC error */
287 #define FMDMSR_WRB_SECC		0x02000000 /* write buf ECC err sys side */
288 #define FMDMSR_WRB_FECC		0x01000000 /* write buf ECC err Fman side */
289 #define FMDMSR_DPEXT_SECC	0x00800000 /* DP external ECC err sys side */
290 #define FMDMSR_DPEXT_FECC	0x00400000 /* DP external ECC err Fman side */
291 #define FMDMSR_DPDAT_SECC	0x00200000 /* DP data ECC err on sys side */
292 #define FMDMSR_DPDAT_FECC	0x00100000 /* DP data ECC err on Fman side */
293 #define FMDMSR_SPDAT_FECC	0x00080000 /* SP data ECC error Fman side */
301 /* FMDMMR - FMan DMA mode register */
313 	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
315 	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
323 	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
333 	u32	fpmcev[0x4];	/* CPU event 0-3 */
341 /* FMFP_PRC - FPM Port_ID Control Register */
352 /* FMFP_EE - FPM event and enable register */
353 #define FMFPEE_DECC		0x80000000 /* double ECC err on FPM ram */
355 #define FMFPEE_SECC		0x20000000 /* single ECC error */
357 #define FMFPEE_DECC_EN		0x00008000 /* double ECC interrupt enable */
359 #define FMFPEE_SECC_EN		0x00002000 /* single ECC err interrupt enable */
369 /* FMFP_RCR - FMan Rams Control and Event */
370 #define FMFP_RCR_MDEC		0x00008000 /* double ECC error in muram */
371 #define FMFP_RCR_IDEC		0x00004000 /* double ECC error in iram */
399 	u8	res1[0x1000 - 0x138];