Lines Matching +full:ecc +full:- +full:engine

16 	  EDAC is a subsystem along with hardware-specific drivers designed to
17 	  report hardware errors. These are low-level errors that are reported
22 	  The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 	  levels are 0-4 (from low to high) and by default it is set to 2.
44 	tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 	  occurring on your machine in human-readable form.
59 	  Not all machines support hardware-driven error report. Some of those
60 	  provide a BIOS-driven error report mechanism via ACPI, using the
64 	  When this option is enabled, it will disable the hardware-driven
68 	  It should be noticed that keeping both GHES and a hardware-driven
81 	  Support for error detection and correction of DRAM ECC errors on
89 	  Injection into the ECC detection circuits. The amd64_edac module
96 	  - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 	  - inject_word (0..8, 16-bit word of 16-byte section),
98 	  - inject_ecc_vector (hex ecc vector: select bits of inject word)
101 	  which trigger the DRAM ECC Read and Write respectively.
172 	  E3-1200 based DRAM controllers.
233 	tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
248 	  system has non-volatile DIMMs you should also manually
260 	  system has non-volatile DIMMs you should also manually
270 	  micro-server but may appear on others in the future.
301 	tristate "Cell Broadband Engine memory controller"
305 	  Cell Broadband Engine internal memory controller
312 	  This enables support for EDAC on the ECC memory used
318 	tristate "AMD8131 HyperTransport PCI-X Tunnel"
322 	  AMD8131 HyperTransport PCI-X Tunnel chip.
397 	bool "Altera SOCFPGA ECC"
405 	bool "Altera SDRAM ECC"
414 	bool "Altera L2 Cache ECC"
422 	bool "Altera On-Chip RAM ECC"
426 	  Altera On-Chip RAM Memory for Altera SoCs.
429 	bool "Altera Ethernet FIFO ECC"
436 	bool "Altera NAND FIFO ECC"
443 	bool "Altera DMA FIFO ECC"
450 	bool "Altera USB FIFO ECC"
457 	bool "Altera QSPI FIFO ECC"
464 	bool "Altera SDMMC FIFO ECC"
477 	bool "Marvell Armada XP DDR and L2 Cache ECC"
491 	tristate "APM X-Gene SoC"
495 	  APM X-Gene family of SOCs.
498 	tristate "Texas Instruments DDR3 ECC Controller"
523 	  First, ECC must be configured in the bootloader. Then, this driver
527 	tristate "Mellanox BlueField Memory ECC"
534 	tristate "ARM DMC-520 ECC"
538 	  SoCs with ARM DMC-520 DRAM controller.