u-boot/doc/README.nand

8 # SPDX-License-Identifier:	GPL-2.0+
32       If `clean' is specified, a JFFS2-style clean marker is written to
49       Read `size' bytes from the out-of-band data area corresponding to
51       data for one 512-byte page or 2 256-byte pages. There is no check
52       for bad blocks or ECC errors.
68       described above -- with the additional check that all pages at the end
73       [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
76       Write `size' bytes from `addr' to the out-of-band data area
78       of data for one 512-byte page or 2 256-byte pages. There is no check
84       "addr" in memory.  This is a raw access, so ECC is avoided and the
87       a packed sequence of "data, oob, data, oob, ..." -- no alignment of
93 	NAND Offset from where SPL will read u-boot image. This is the starting
94 	address of u-boot MTD partition in NAND.
106       If specified, overrides the maximum number of ECC bytes
120       the initialization process -- it provides the mtd and nand
132       tasks except setting mtd->name, and registering with the rest of
133       U-Boot.  Those last tasks are accomplished by calling  nand_register()
163 	 * and in mtd->name.  Must be less than CONFIG_SYS_MAX_NAND_DEVICE.
169       the difference between a U-Boot driver and its Linux counterpart.
188 	do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
189 	and BCH16 ECC algorithms.
193 	ELM controller is used for ECC error detection (not ECC calculation)
194 	of BCH4, BCH8 and BCH16 ECC algorithms.
195 	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
196 	thus such SoC platforms need to depend on software library for ECC error
197 	detection. However ECC calculation on such plaforms would still be
201 	Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
202         hardware ECC correction. This is useful for platforms which have ELM
203 	hardware engine and use NAND boot mode.
204 	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
206         SPL-NAND driver with software ECC correction support.
209 	On OMAP platforms, this CONFIG specifies NAND ECC scheme.
212 		1-bit Hamming code using software lib.
215 		1-bit Hamming code using GPMC hardware.
218 		4-bit BCH code (unsupported)
220 		4-bit BCH code (unsupported)
222 		8-bit BCH code with
223 		- ecc calculation using GPMC hardware engine,
224 		- error detection using software library.
225 		- requires CONFIG_BCH to enable software BCH library
226 		(For legacy device which do not have ELM h/w engine)
228 		8-bit BCH code with
229 		- ecc calculation using GPMC hardware engine,
230 		- error detection using ELM hardware engine.
232 		16-bit BCH code with
233 		- ecc calculation using GPMC hardware engine,
234 		- error detection using ELM hardware engine.
236 	How to select ECC scheme on OMAP and AMxx platforms ?
237 	-----------------------------------------------------
238 	Though higher ECC schemes have more capability to detect and correct
239 	bit-flips, but still selection of ECC scheme is dependent on following
240 	- hardware engines present in SoC.
241 		Some legacy OMAP SoC do not have ELM h/w engine thus such
242 		SoC cannot support BCHx_HW ECC schemes.
243 	- size of OOB/Spare region
244 		With higher ECC schemes, more OOB/Spare area is required to
245 		store ECC. So choice of ECC scheme is limited by NAND oobsize.
252 		NAND_PAGESIZE	= bytes in main-area of NAND page.
253 		ECC_BYTES	= number of ECC bytes generated to
255 				3 for HAM1_xx ecc schemes
256 				7 for BCH4_xx ecc schemes
257 				14 for BCH8_xx ecc schemes
258 				26 for BCH16_xx ecc schemes
284 the current NAND system but has not yet been adapted to the u-boot
287 Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
293   "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
318   automate actions following a nand->write() error. This would e.g. be required