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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Chen-Yu Tsai <wens@csie.org>
15 - Maxime Ripard <mripard@kernel.org>
20 - const: allwinner,sun4i-a10-hdmi
21 - const: allwinner,sun5i-a10s-hdmi
22 - const: allwinner,sun6i-a31-hdmi
23 - items:
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H A Dst,stih4xx.txt3 - sti-vtg: video timing generator
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP registers and length of memory mapped region.
8 - interrupts : VTG interrupt number to the CPU.
9 - st,slave: phandle on a slave vtg
11 - sti-vtac: video timing advanced inter dye communication Rx and TX
13 - compatible: "st,vtac-main" or "st,vtac-aux"
14 - reg: Physical base address of the IP registers and length of memory mapped region.
15 - clocks: from common clock binding: handle hardware IP needed clocks, the
17 See ../clocks/clock-bindings.txt for details.
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H A Damlogic,meson-dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Neil Armstrong <narmstrong@baylibre.com>
14 - $ref: /schemas/sound/name-prefix.yaml#
18 - A Synopsys DesignWare HDMI Controller IP
19 - A TOP control block controlling the Clocks and PHY
20 - A custom HDMI PHY in order to convert video to TMDS signal
27 |___________________________________|<=> DDC
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,hdmi.txt8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - the supported chips are mt2701, mt7623 and mt8173
10 - reg: Physical base address and length of the controller's registers
11 - interrupts: The interrupt signal from the function block.
12 - clocks: device clocks
13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
15 - phys: phandle link to the HDMI PHY node.
16 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
17 - phy-names: must contain "hdmi"
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/imx/
H A Dhdmi.txt1 Freescale i.MX6 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
15 - reg: See dw_hdmi.txt.
16 - interrupts: HDMI interrupt number
17 - clocks: See dw_hdmi.txt.
18 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
19 - ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/
H A Ddw_hdmi-rockchip.txt1 Rockchip DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible: should be one of the following:
15 "rockchip,rk3228-dw-hdmi"
16 "rockchip,rk3288-dw-hdmi"
17 "rockchip,rk3328-dw-hdmi"
18 "rockchip,rk3368-dw-hdmi"
19 "rockchip,rk3399-dw-hdmi"
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/
H A Dhdmi.txt4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
13 - interrupts: The interrupt signal from the hdmi block.
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
243 /* LM DDC, default value: 0x80 */
252 /* DDC I2C Manual, default value: 0x03 */
263 /* DDC I2C Target Slave Address, default value: 0x00 */
267 /* DDC I2C Target Segment Address, default value: 0x00 */
270 /* DDC I2C Target Offset Address, default value: 0x00 */
273 /* DDC I2C Data In count #1, default value: 0x00 */
276 /* DDC I2C Data In count #2, default value: 0x00 */
280 /* DDC I2C Status, default value: 0x04 */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/zte/
H A Dzx_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <sound/hdmi-codec.h>
41 struct zx_hdmi_i2c *ddc; member
57 return readl_relaxed(hdmi->mmio + offset * 4); in hdmi_readb()
62 writel_relaxed(val, hdmi->mmio + offset * 4); in hdmi_writeb()
86 DRM_DEV_ERROR(hdmi->dev, "failed to pack infoframe: %d\n", num); in zx_hdmi_infoframe_trans()
108 &hdmi->connector, in zx_hdmi_config_video_vsi()
111 DRM_DEV_ERROR(hdmi->dev, "failed to get vendor infoframe: %d\n", in zx_hdmi_config_video_vsi()
126 &hdmi->connector, in zx_hdmi_config_video_avi()
129 DRM_DEV_ERROR(hdmi->dev, "failed to get avi infoframe: %d\n", in zx_hdmi_config_video_avi()
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/OK3568_Linux_fs/kernel/drivers/media/i2c/it66353/
H A Dit66353.c1 // SPDX-License-Identifier: GPL-2.0
8 * Wangqiang Guo<kay.guo@rock-chips.com>
28 #include <linux/i2c-dev.h>
58 #define PR_IO(x) { if (g_enable_io_log) dev_dbg(g_it66353->dev, x); }
107 struct i2c_client *client = it66353->client; in i2c_wr()
113 msg.addr = client->addr; in i2c_wr()
117 err = i2c_transfer(client->adapter, &msg, 1); in i2c_wr()
119 dev_err(it66353->dev, "writing register 0x%x from 0x%x failed\n", in i2c_wr()
120 reg, client->addr); in i2c_wr()
124 dev_dbg(it66353->dev, "I2C write 0x%02x = 0x%02x\n", in i2c_wr()
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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H A Dsun5i-a10s.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/dma/sun4i-a10.h>
55 #address-cells = <1>;
56 #size-cells = <1>;
59 framebuffer-lcd0-hdmi {
60 compatible = "allwinner,simple-framebuffer",
61 "simple-framebuffer";
62 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 display-engine {
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H A Dbcm2835-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 interrupt-parent = <&intc>;
12 compatible = "brcm,bcm2835-dma";
25 /* dma channel 11-14 share one irq */
32 interrupt-names = "dma0",
47 "dma-shared-all";
48 #dma-cells = <1>;
49 brcm,dma-channel-mask = <0x7f35>;
52 intc: interrupt-controller@7e00b200 {
53 compatible = "brcm,bcm2835-armctrl-ic";
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H A Drk3288-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
11 hdmi_gpio: hdmi-gpio {
17 hdmi_cec_c0: hdmi-cec-c0 {
22 hdmi_cec_c7: hdmi-cec-c7 {
27 hdmi_ddc: hdmi-ddc {
33 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
41 global_pwroff: global-pwroff {
46 ddrio_pwroff: ddrio-pwroff {
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H A Drk628.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/reset/rk628-rgu.h>
5 #include <dt-bindings/clock/rk628-cgu.h>
8 rk628_xin_osc0_func: rk628-xin-osc0-func {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <24000000>;
12 clock-output-names = "rk628_xin_osc0_func";
15 rk628_xin_osc0_half: rk628-xin-osc0-half {
16 compatible = "fixed-factor-clock";
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H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/reset/sun6i-a31-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
61 #address-cells = <1>;
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dmeson-gxbb-odroidc2.dts6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
47 #include "meson-gxbb.dtsi"
48 #include <dt-bindings/gpio/gpio.h>
51 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
52 model = "Hardkernel ODROID-C2";
59 stdout-path = "serial0:115200n8";
67 usb_otg_pwr: regulator-usb-pwrs {
68 compatible = "regulator-fixed";
70 regulator-name = "USB_OTG_PWR";
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
21 stdout-path = "serial0:115200n8";
30 compatible = "gpio-leds";
32 led-stat {
33 label = "nanopi-k2:blue:stat";
35 default-state = "on";
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H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
15 model = "Hardkernel ODROID-C2";
23 stdout-path = "serial0:115200n8";
31 usb_otg_pwr: regulator-usb-pwrs {
32 compatible = "regulator-fixed";
34 regulator-name = "USB_OTG_PWR";
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_aux.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
216 * 2.3.4 "Detailed uPacket TX AUX CH State Description".
225 * EPR #379763: by trial-and-error on different systems,
229 * AUX Error or AUX Timeout conditions - not during normal operation.
243 struct ddc *ddc; member
301 struct ddc *ddc);
303 int dce_aux_transfer_raw(struct ddc_service *ddc,
307 bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
312 (struct ddc_service *ddc,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
15 #include <media/cec-pin.h>
37 #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))
38 #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)
135 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1)
138 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1)
143 #define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1)
187 /* DDC CLK bit fields are the same, but the formula is not */
226 /* DDC FIFO register offset */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/hdmi/
H A Dhdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <sound/hdmi-codec.h>
19 spin_lock_irqsave(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
22 if (!hdmi->hdmi_mode) { in msm_hdmi_set_mode()
34 spin_unlock_irqrestore(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
44 msm_hdmi_connector_irq(hdmi->connector); in msm_hdmi_irq()
46 /* Process DDC: */ in msm_hdmi_irq()
47 msm_hdmi_i2c_irq(hdmi->i2c); in msm_hdmi_irq()
50 if (hdmi->hdcp_ctrl) in msm_hdmi_irq()
51 msm_hdmi_hdcp_irq(hdmi->hdcp_ctrl); in msm_hdmi_irq()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c2 * Copyright © 2006-2007 Intel Corporation
56 int tx; member
101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_hw_state()
102 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_lvds_get_hw_state()
107 encoder->power_domain); in intel_lvds_get_hw_state()
111 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); in intel_lvds_get_hw_state()
113 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_lvds_get_hw_state()
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_config()
122 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_lvds_get_config()
125 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
13 #include <linux/extcon-provider.h>
21 #include <linux/dma-mapping.h>
25 #include <media/cec-notifier.h>
27 #include <uapi/linux/media-bus-format.h>
40 #include "dw-hdmi-audio.h"
41 #include "dw-hdmi-cec.h"
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H A Ddw-hdmi-qp.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Algea Cao <algea.cao@rock-chips.com>
9 #include <linux/dma-mapping.h>
11 #include <linux/extcon-provider.h>
35 #include <uapi/linux/media-bus-format.h>
38 #include "dw-hdmi-qp-audio.h"
39 #include "dw-hdmi-qp.h"
40 #include "dw-hdmi-qp-cec.h"
42 #include <media/cec-notifier.h>
49 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
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