xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/zte/zx_hdmi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2016 Linaro Ltd.
4*4882a593Smuzhiyun  * Copyright 2016 ZTE Corporation.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/clk.h>
8*4882a593Smuzhiyun #include <linux/component.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/hdmi.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/mutex.h>
16*4882a593Smuzhiyun #include <linux/of_device.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
19*4882a593Smuzhiyun #include <drm/drm_edid.h>
20*4882a593Smuzhiyun #include <drm/drm_of.h>
21*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
22*4882a593Smuzhiyun #include <drm/drm_print.h>
23*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <sound/hdmi-codec.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "zx_hdmi_regs.h"
28*4882a593Smuzhiyun #include "zx_vou.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define ZX_HDMI_INFOFRAME_SIZE		31
31*4882a593Smuzhiyun #define DDC_SEGMENT_ADDR		0x30
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun struct zx_hdmi_i2c {
34*4882a593Smuzhiyun 	struct i2c_adapter adap;
35*4882a593Smuzhiyun 	struct mutex lock;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun struct zx_hdmi {
39*4882a593Smuzhiyun 	struct drm_connector connector;
40*4882a593Smuzhiyun 	struct drm_encoder encoder;
41*4882a593Smuzhiyun 	struct zx_hdmi_i2c *ddc;
42*4882a593Smuzhiyun 	struct device *dev;
43*4882a593Smuzhiyun 	struct drm_device *drm;
44*4882a593Smuzhiyun 	void __iomem *mmio;
45*4882a593Smuzhiyun 	struct clk *cec_clk;
46*4882a593Smuzhiyun 	struct clk *osc_clk;
47*4882a593Smuzhiyun 	struct clk *xclk;
48*4882a593Smuzhiyun 	bool sink_is_hdmi;
49*4882a593Smuzhiyun 	bool sink_has_audio;
50*4882a593Smuzhiyun 	struct platform_device *audio_pdev;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define to_zx_hdmi(x) container_of(x, struct zx_hdmi, x)
54*4882a593Smuzhiyun 
hdmi_readb(struct zx_hdmi * hdmi,u16 offset)55*4882a593Smuzhiyun static inline u8 hdmi_readb(struct zx_hdmi *hdmi, u16 offset)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	return readl_relaxed(hdmi->mmio + offset * 4);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
hdmi_writeb(struct zx_hdmi * hdmi,u16 offset,u8 val)60*4882a593Smuzhiyun static inline void hdmi_writeb(struct zx_hdmi *hdmi, u16 offset, u8 val)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	writel_relaxed(val, hdmi->mmio + offset * 4);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
hdmi_writeb_mask(struct zx_hdmi * hdmi,u16 offset,u8 mask,u8 val)65*4882a593Smuzhiyun static inline void hdmi_writeb_mask(struct zx_hdmi *hdmi, u16 offset,
66*4882a593Smuzhiyun 				    u8 mask, u8 val)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	u8 tmp;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	tmp = hdmi_readb(hdmi, offset);
71*4882a593Smuzhiyun 	tmp = (tmp & ~mask) | (val & mask);
72*4882a593Smuzhiyun 	hdmi_writeb(hdmi, offset, tmp);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
zx_hdmi_infoframe_trans(struct zx_hdmi * hdmi,union hdmi_infoframe * frame,u8 fsel)75*4882a593Smuzhiyun static int zx_hdmi_infoframe_trans(struct zx_hdmi *hdmi,
76*4882a593Smuzhiyun 				   union hdmi_infoframe *frame, u8 fsel)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	u8 buffer[ZX_HDMI_INFOFRAME_SIZE];
79*4882a593Smuzhiyun 	int num;
80*4882a593Smuzhiyun 	int i;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	hdmi_writeb(hdmi, TPI_INFO_FSEL, fsel);
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	num = hdmi_infoframe_pack(frame, buffer, ZX_HDMI_INFOFRAME_SIZE);
85*4882a593Smuzhiyun 	if (num < 0) {
86*4882a593Smuzhiyun 		DRM_DEV_ERROR(hdmi->dev, "failed to pack infoframe: %d\n", num);
87*4882a593Smuzhiyun 		return num;
88*4882a593Smuzhiyun 	}
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	for (i = 0; i < num; i++)
91*4882a593Smuzhiyun 		hdmi_writeb(hdmi, TPI_INFO_B0 + i, buffer[i]);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_RPT,
94*4882a593Smuzhiyun 			 TPI_INFO_TRANS_RPT);
95*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, TPI_INFO_EN, TPI_INFO_TRANS_EN,
96*4882a593Smuzhiyun 			 TPI_INFO_TRANS_EN);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	return num;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
zx_hdmi_config_video_vsi(struct zx_hdmi * hdmi,struct drm_display_mode * mode)101*4882a593Smuzhiyun static int zx_hdmi_config_video_vsi(struct zx_hdmi *hdmi,
102*4882a593Smuzhiyun 				    struct drm_display_mode *mode)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	union hdmi_infoframe frame;
105*4882a593Smuzhiyun 	int ret;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
108*4882a593Smuzhiyun 							  &hdmi->connector,
109*4882a593Smuzhiyun 							  mode);
110*4882a593Smuzhiyun 	if (ret) {
111*4882a593Smuzhiyun 		DRM_DEV_ERROR(hdmi->dev, "failed to get vendor infoframe: %d\n",
112*4882a593Smuzhiyun 			      ret);
113*4882a593Smuzhiyun 		return ret;
114*4882a593Smuzhiyun 	}
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_VSIF);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
zx_hdmi_config_video_avi(struct zx_hdmi * hdmi,struct drm_display_mode * mode)119*4882a593Smuzhiyun static int zx_hdmi_config_video_avi(struct zx_hdmi *hdmi,
120*4882a593Smuzhiyun 				    struct drm_display_mode *mode)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	union hdmi_infoframe frame;
123*4882a593Smuzhiyun 	int ret;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
126*4882a593Smuzhiyun 						       &hdmi->connector,
127*4882a593Smuzhiyun 						       mode);
128*4882a593Smuzhiyun 	if (ret) {
129*4882a593Smuzhiyun 		DRM_DEV_ERROR(hdmi->dev, "failed to get avi infoframe: %d\n",
130*4882a593Smuzhiyun 			      ret);
131*4882a593Smuzhiyun 		return ret;
132*4882a593Smuzhiyun 	}
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	/* We always use YUV444 for HDMI output. */
135*4882a593Smuzhiyun 	frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_AVI);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
zx_hdmi_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adj_mode)140*4882a593Smuzhiyun static void zx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
141*4882a593Smuzhiyun 				     struct drm_display_mode *mode,
142*4882a593Smuzhiyun 				     struct drm_display_mode *adj_mode)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	if (hdmi->sink_is_hdmi) {
147*4882a593Smuzhiyun 		zx_hdmi_config_video_avi(hdmi, mode);
148*4882a593Smuzhiyun 		zx_hdmi_config_video_vsi(hdmi, mode);
149*4882a593Smuzhiyun 	}
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
zx_hdmi_phy_start(struct zx_hdmi * hdmi)152*4882a593Smuzhiyun static void zx_hdmi_phy_start(struct zx_hdmi *hdmi)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	/* Copy from ZTE BSP code */
155*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x222, 0x0);
156*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x224, 0x4);
157*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x909, 0x0);
158*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b0, 0x90);
159*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b1, 0x00);
160*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b2, 0xa7);
161*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b8, 0xaa);
162*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b2, 0xa7);
163*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b3, 0x0f);
164*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b4, 0x0f);
165*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b5, 0x55);
166*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b7, 0x03);
167*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b9, 0x12);
168*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7ba, 0x32);
169*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7bc, 0x68);
170*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7be, 0x40);
171*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7bf, 0x84);
172*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7c1, 0x0f);
173*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7c8, 0x02);
174*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7c9, 0x03);
175*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7ca, 0x40);
176*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7dc, 0x31);
177*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7e2, 0x04);
178*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7e0, 0x06);
179*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7cb, 0x68);
180*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7f9, 0x02);
181*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7b6, 0x02);
182*4882a593Smuzhiyun 	hdmi_writeb(hdmi, 0x7f3, 0x0);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun 
zx_hdmi_hw_enable(struct zx_hdmi * hdmi)185*4882a593Smuzhiyun static void zx_hdmi_hw_enable(struct zx_hdmi *hdmi)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	/* Enable pclk */
188*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, CLKPWD_PDIDCK);
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	/* Enable HDMI for TX */
191*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, FUNC_HDMI_EN);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	/* Enable deep color packet */
194*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	/* Enable HDMI/MHL mode for output */
197*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, TEST_TXCTRL, TEST_TXCTRL_HDMI_MODE,
198*4882a593Smuzhiyun 			 TEST_TXCTRL_HDMI_MODE);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* Configure reg_qc_sel */
201*4882a593Smuzhiyun 	hdmi_writeb(hdmi, HDMICTL4, 0x3);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	/* Enable interrupt */
204*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT,
205*4882a593Smuzhiyun 			 INTR1_MONITOR_DETECT);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* Start up phy */
208*4882a593Smuzhiyun 	zx_hdmi_phy_start(hdmi);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
zx_hdmi_hw_disable(struct zx_hdmi * hdmi)211*4882a593Smuzhiyun static void zx_hdmi_hw_disable(struct zx_hdmi *hdmi)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	/* Disable interrupt */
214*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, INTR1_MASK, INTR1_MONITOR_DETECT, 0);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	/* Disable deep color packet */
217*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, P2T_CTRL, P2T_DC_PKT_EN, P2T_DC_PKT_EN);
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	/* Disable HDMI for TX */
220*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, FUNC_SEL, FUNC_HDMI_EN, 0);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	/* Disable pclk */
223*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, CLKPWD, CLKPWD_PDIDCK, 0);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
zx_hdmi_encoder_enable(struct drm_encoder * encoder)226*4882a593Smuzhiyun static void zx_hdmi_encoder_enable(struct drm_encoder *encoder)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	clk_prepare_enable(hdmi->cec_clk);
231*4882a593Smuzhiyun 	clk_prepare_enable(hdmi->osc_clk);
232*4882a593Smuzhiyun 	clk_prepare_enable(hdmi->xclk);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	zx_hdmi_hw_enable(hdmi);
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	vou_inf_enable(VOU_HDMI, encoder->crtc);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun 
zx_hdmi_encoder_disable(struct drm_encoder * encoder)239*4882a593Smuzhiyun static void zx_hdmi_encoder_disable(struct drm_encoder *encoder)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = to_zx_hdmi(encoder);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	vou_inf_disable(VOU_HDMI, encoder->crtc);
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	zx_hdmi_hw_disable(hdmi);
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	clk_disable_unprepare(hdmi->xclk);
248*4882a593Smuzhiyun 	clk_disable_unprepare(hdmi->osc_clk);
249*4882a593Smuzhiyun 	clk_disable_unprepare(hdmi->cec_clk);
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs zx_hdmi_encoder_helper_funcs = {
253*4882a593Smuzhiyun 	.enable	= zx_hdmi_encoder_enable,
254*4882a593Smuzhiyun 	.disable = zx_hdmi_encoder_disable,
255*4882a593Smuzhiyun 	.mode_set = zx_hdmi_encoder_mode_set,
256*4882a593Smuzhiyun };
257*4882a593Smuzhiyun 
zx_hdmi_connector_get_modes(struct drm_connector * connector)258*4882a593Smuzhiyun static int zx_hdmi_connector_get_modes(struct drm_connector *connector)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = to_zx_hdmi(connector);
261*4882a593Smuzhiyun 	struct edid *edid;
262*4882a593Smuzhiyun 	int ret;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	edid = drm_get_edid(connector, &hdmi->ddc->adap);
265*4882a593Smuzhiyun 	if (!edid)
266*4882a593Smuzhiyun 		return 0;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
269*4882a593Smuzhiyun 	hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
270*4882a593Smuzhiyun 	drm_connector_update_edid_property(connector, edid);
271*4882a593Smuzhiyun 	ret = drm_add_edid_modes(connector, edid);
272*4882a593Smuzhiyun 	kfree(edid);
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	return ret;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun static enum drm_mode_status
zx_hdmi_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)278*4882a593Smuzhiyun zx_hdmi_connector_mode_valid(struct drm_connector *connector,
279*4882a593Smuzhiyun 			     struct drm_display_mode *mode)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun 	return MODE_OK;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun static struct drm_connector_helper_funcs zx_hdmi_connector_helper_funcs = {
285*4882a593Smuzhiyun 	.get_modes = zx_hdmi_connector_get_modes,
286*4882a593Smuzhiyun 	.mode_valid = zx_hdmi_connector_mode_valid,
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun static enum drm_connector_status
zx_hdmi_connector_detect(struct drm_connector * connector,bool force)290*4882a593Smuzhiyun zx_hdmi_connector_detect(struct drm_connector *connector, bool force)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = to_zx_hdmi(connector);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	return (hdmi_readb(hdmi, TPI_HPD_RSEN) & TPI_HPD_CONNECTION) ?
295*4882a593Smuzhiyun 		connector_status_connected : connector_status_disconnected;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun static const struct drm_connector_funcs zx_hdmi_connector_funcs = {
299*4882a593Smuzhiyun 	.fill_modes = drm_helper_probe_single_connector_modes,
300*4882a593Smuzhiyun 	.detect = zx_hdmi_connector_detect,
301*4882a593Smuzhiyun 	.destroy = drm_connector_cleanup,
302*4882a593Smuzhiyun 	.reset = drm_atomic_helper_connector_reset,
303*4882a593Smuzhiyun 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
304*4882a593Smuzhiyun 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
zx_hdmi_register(struct drm_device * drm,struct zx_hdmi * hdmi)307*4882a593Smuzhiyun static int zx_hdmi_register(struct drm_device *drm, struct zx_hdmi *hdmi)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun 	struct drm_encoder *encoder = &hdmi->encoder;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	encoder->possible_crtcs = VOU_CRTC_MASK;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
314*4882a593Smuzhiyun 	drm_encoder_helper_add(encoder, &zx_hdmi_encoder_helper_funcs);
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	drm_connector_init_with_ddc(drm, &hdmi->connector,
319*4882a593Smuzhiyun 				    &zx_hdmi_connector_funcs,
320*4882a593Smuzhiyun 				    DRM_MODE_CONNECTOR_HDMIA,
321*4882a593Smuzhiyun 				    &hdmi->ddc->adap);
322*4882a593Smuzhiyun 	drm_connector_helper_add(&hdmi->connector,
323*4882a593Smuzhiyun 				 &zx_hdmi_connector_helper_funcs);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	drm_connector_attach_encoder(&hdmi->connector, encoder);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	return 0;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun 
zx_hdmi_irq_thread(int irq,void * dev_id)330*4882a593Smuzhiyun static irqreturn_t zx_hdmi_irq_thread(int irq, void *dev_id)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = dev_id;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	drm_helper_hpd_irq_event(hdmi->connector.dev);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	return IRQ_HANDLED;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun 
zx_hdmi_irq_handler(int irq,void * dev_id)339*4882a593Smuzhiyun static irqreturn_t zx_hdmi_irq_handler(int irq, void *dev_id)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = dev_id;
342*4882a593Smuzhiyun 	u8 lstat;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	lstat = hdmi_readb(hdmi, L1_INTR_STAT);
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	/* Monitor detect/HPD interrupt */
347*4882a593Smuzhiyun 	if (lstat & L1_INTR_STAT_INTR1) {
348*4882a593Smuzhiyun 		u8 stat;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 		stat = hdmi_readb(hdmi, INTR1_STAT);
351*4882a593Smuzhiyun 		hdmi_writeb(hdmi, INTR1_STAT, stat);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 		if (stat & INTR1_MONITOR_DETECT)
354*4882a593Smuzhiyun 			return IRQ_WAKE_THREAD;
355*4882a593Smuzhiyun 	}
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	return IRQ_NONE;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
zx_hdmi_audio_startup(struct device * dev,void * data)360*4882a593Smuzhiyun static int zx_hdmi_audio_startup(struct device *dev, void *data)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = dev_get_drvdata(dev);
363*4882a593Smuzhiyun 	struct drm_encoder *encoder = &hdmi->encoder;
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	vou_inf_hdmi_audio_sel(encoder->crtc, VOU_HDMI_AUD_SPDIF);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	return 0;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
zx_hdmi_audio_shutdown(struct device * dev,void * data)370*4882a593Smuzhiyun static void zx_hdmi_audio_shutdown(struct device *dev, void *data)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = dev_get_drvdata(dev);
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	/* Disable audio input */
375*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, AUD_EN, AUD_IN_EN, 0);
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
zx_hdmi_audio_get_n(unsigned int fs)378*4882a593Smuzhiyun static inline int zx_hdmi_audio_get_n(unsigned int fs)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun 	unsigned int n;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	if (fs && (fs % 44100) == 0)
383*4882a593Smuzhiyun 		n = 6272 * (fs / 44100);
384*4882a593Smuzhiyun 	else
385*4882a593Smuzhiyun 		n = fs * 128 / 1000;
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	return n;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
zx_hdmi_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)390*4882a593Smuzhiyun static int zx_hdmi_audio_hw_params(struct device *dev,
391*4882a593Smuzhiyun 				   void *data,
392*4882a593Smuzhiyun 				   struct hdmi_codec_daifmt *daifmt,
393*4882a593Smuzhiyun 				   struct hdmi_codec_params *params)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = dev_get_drvdata(dev);
396*4882a593Smuzhiyun 	struct hdmi_audio_infoframe *cea = &params->cea;
397*4882a593Smuzhiyun 	union hdmi_infoframe frame;
398*4882a593Smuzhiyun 	int n;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	/* We only support spdif for now */
401*4882a593Smuzhiyun 	if (daifmt->fmt != HDMI_SPDIF) {
402*4882a593Smuzhiyun 		DRM_DEV_ERROR(hdmi->dev, "invalid daifmt %d\n", daifmt->fmt);
403*4882a593Smuzhiyun 		return -EINVAL;
404*4882a593Smuzhiyun 	}
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	switch (params->sample_width) {
407*4882a593Smuzhiyun 	case 16:
408*4882a593Smuzhiyun 		hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
409*4882a593Smuzhiyun 				 SPDIF_SAMPLE_SIZE_16BIT);
410*4882a593Smuzhiyun 		break;
411*4882a593Smuzhiyun 	case 20:
412*4882a593Smuzhiyun 		hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
413*4882a593Smuzhiyun 				 SPDIF_SAMPLE_SIZE_20BIT);
414*4882a593Smuzhiyun 		break;
415*4882a593Smuzhiyun 	case 24:
416*4882a593Smuzhiyun 		hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, SPDIF_SAMPLE_SIZE_MASK,
417*4882a593Smuzhiyun 				 SPDIF_SAMPLE_SIZE_24BIT);
418*4882a593Smuzhiyun 		break;
419*4882a593Smuzhiyun 	default:
420*4882a593Smuzhiyun 		DRM_DEV_ERROR(hdmi->dev, "invalid sample width %d\n",
421*4882a593Smuzhiyun 			      params->sample_width);
422*4882a593Smuzhiyun 		return -EINVAL;
423*4882a593Smuzhiyun 	}
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	/* CTS is calculated by hardware, and we only need to take care of N */
426*4882a593Smuzhiyun 	n = zx_hdmi_audio_get_n(params->sample_rate);
427*4882a593Smuzhiyun 	hdmi_writeb(hdmi, N_SVAL1, n & 0xff);
428*4882a593Smuzhiyun 	hdmi_writeb(hdmi, N_SVAL2, (n >> 8) & 0xff);
429*4882a593Smuzhiyun 	hdmi_writeb(hdmi, N_SVAL3, (n >> 16) & 0xf);
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	/* Enable spdif mode */
432*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, AUD_MODE, SPDIF_EN, SPDIF_EN);
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	/* Enable audio input */
435*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, AUD_EN, AUD_IN_EN, AUD_IN_EN);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	memcpy(&frame.audio, cea, sizeof(*cea));
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	return zx_hdmi_infoframe_trans(hdmi, &frame, FSEL_AUDIO);
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun 
zx_hdmi_audio_mute(struct device * dev,void * data,bool enable,int direction)442*4882a593Smuzhiyun static int zx_hdmi_audio_mute(struct device *dev, void *data,
443*4882a593Smuzhiyun 			      bool enable, int direction)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = dev_get_drvdata(dev);
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	if (enable)
448*4882a593Smuzhiyun 		hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, TPI_AUD_MUTE,
449*4882a593Smuzhiyun 				 TPI_AUD_MUTE);
450*4882a593Smuzhiyun 	else
451*4882a593Smuzhiyun 		hdmi_writeb_mask(hdmi, TPI_AUD_CONFIG, TPI_AUD_MUTE, 0);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	return 0;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun 
zx_hdmi_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)456*4882a593Smuzhiyun static int zx_hdmi_audio_get_eld(struct device *dev, void *data,
457*4882a593Smuzhiyun 				 uint8_t *buf, size_t len)
458*4882a593Smuzhiyun {
459*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = dev_get_drvdata(dev);
460*4882a593Smuzhiyun 	struct drm_connector *connector = &hdmi->connector;
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	return 0;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun static const struct hdmi_codec_ops zx_hdmi_codec_ops = {
468*4882a593Smuzhiyun 	.audio_startup = zx_hdmi_audio_startup,
469*4882a593Smuzhiyun 	.hw_params = zx_hdmi_audio_hw_params,
470*4882a593Smuzhiyun 	.audio_shutdown = zx_hdmi_audio_shutdown,
471*4882a593Smuzhiyun 	.mute_stream = zx_hdmi_audio_mute,
472*4882a593Smuzhiyun 	.get_eld = zx_hdmi_audio_get_eld,
473*4882a593Smuzhiyun 	.no_capture_mute = 1,
474*4882a593Smuzhiyun };
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun static struct hdmi_codec_pdata zx_hdmi_codec_pdata = {
477*4882a593Smuzhiyun 	.ops = &zx_hdmi_codec_ops,
478*4882a593Smuzhiyun 	.spdif = 1,
479*4882a593Smuzhiyun };
480*4882a593Smuzhiyun 
zx_hdmi_audio_register(struct zx_hdmi * hdmi)481*4882a593Smuzhiyun static int zx_hdmi_audio_register(struct zx_hdmi *hdmi)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun 	struct platform_device *pdev;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	pdev = platform_device_register_data(hdmi->dev, HDMI_CODEC_DRV_NAME,
486*4882a593Smuzhiyun 					     PLATFORM_DEVID_AUTO,
487*4882a593Smuzhiyun 					     &zx_hdmi_codec_pdata,
488*4882a593Smuzhiyun 					     sizeof(zx_hdmi_codec_pdata));
489*4882a593Smuzhiyun 	if (IS_ERR(pdev))
490*4882a593Smuzhiyun 		return PTR_ERR(pdev);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	hdmi->audio_pdev = pdev;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	return 0;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun 
zx_hdmi_i2c_read(struct zx_hdmi * hdmi,struct i2c_msg * msg)497*4882a593Smuzhiyun static int zx_hdmi_i2c_read(struct zx_hdmi *hdmi, struct i2c_msg *msg)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun 	int len = msg->len;
500*4882a593Smuzhiyun 	u8 *buf = msg->buf;
501*4882a593Smuzhiyun 	int retry = 0;
502*4882a593Smuzhiyun 	int ret = 0;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	/* Bits [9:8] of bytes */
505*4882a593Smuzhiyun 	hdmi_writeb(hdmi, ZX_DDC_DIN_CNT2, (len >> 8) & 0xff);
506*4882a593Smuzhiyun 	/* Bits [7:0] of bytes */
507*4882a593Smuzhiyun 	hdmi_writeb(hdmi, ZX_DDC_DIN_CNT1, len & 0xff);
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	/* Clear FIFO */
510*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK, DDC_CMD_CLEAR_FIFO);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	/* Kick off the read */
513*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, ZX_DDC_CMD, DDC_CMD_MASK,
514*4882a593Smuzhiyun 			 DDC_CMD_SEQUENTIAL_READ);
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	while (len > 0) {
517*4882a593Smuzhiyun 		int cnt, i;
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 		/* FIFO needs some time to get ready */
520*4882a593Smuzhiyun 		usleep_range(500, 1000);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 		cnt = hdmi_readb(hdmi, ZX_DDC_DOUT_CNT) & DDC_DOUT_CNT_MASK;
523*4882a593Smuzhiyun 		if (cnt == 0) {
524*4882a593Smuzhiyun 			if (++retry > 5) {
525*4882a593Smuzhiyun 				DRM_DEV_ERROR(hdmi->dev,
526*4882a593Smuzhiyun 					      "DDC FIFO read timed out!");
527*4882a593Smuzhiyun 				return -ETIMEDOUT;
528*4882a593Smuzhiyun 			}
529*4882a593Smuzhiyun 			continue;
530*4882a593Smuzhiyun 		}
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 		for (i = 0; i < cnt; i++)
533*4882a593Smuzhiyun 			*buf++ = hdmi_readb(hdmi, ZX_DDC_DATA);
534*4882a593Smuzhiyun 		len -= cnt;
535*4882a593Smuzhiyun 	}
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	return ret;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun 
zx_hdmi_i2c_write(struct zx_hdmi * hdmi,struct i2c_msg * msg)540*4882a593Smuzhiyun static int zx_hdmi_i2c_write(struct zx_hdmi *hdmi, struct i2c_msg *msg)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun 	/*
543*4882a593Smuzhiyun 	 * The DDC I2C adapter is only for reading EDID data, so we assume
544*4882a593Smuzhiyun 	 * that the write to this adapter must be the EDID data offset.
545*4882a593Smuzhiyun 	 */
546*4882a593Smuzhiyun 	if ((msg->len != 1) ||
547*4882a593Smuzhiyun 	    ((msg->addr != DDC_ADDR) && (msg->addr != DDC_SEGMENT_ADDR)))
548*4882a593Smuzhiyun 		return -EINVAL;
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	if (msg->addr == DDC_SEGMENT_ADDR)
551*4882a593Smuzhiyun 		hdmi_writeb(hdmi, ZX_DDC_SEGM, msg->addr << 1);
552*4882a593Smuzhiyun 	else if (msg->addr == DDC_ADDR)
553*4882a593Smuzhiyun 		hdmi_writeb(hdmi, ZX_DDC_ADDR, msg->addr << 1);
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	hdmi_writeb(hdmi, ZX_DDC_OFFSET, msg->buf[0]);
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	return 0;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun 
zx_hdmi_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)560*4882a593Smuzhiyun static int zx_hdmi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
561*4882a593Smuzhiyun 			    int num)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = i2c_get_adapdata(adap);
564*4882a593Smuzhiyun 	struct zx_hdmi_i2c *ddc = hdmi->ddc;
565*4882a593Smuzhiyun 	int i, ret = 0;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	mutex_lock(&ddc->lock);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	/* Enable DDC master access */
570*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, HW_DDC_MASTER);
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	for (i = 0; i < num; i++) {
573*4882a593Smuzhiyun 		DRM_DEV_DEBUG(hdmi->dev,
574*4882a593Smuzhiyun 			      "xfer: num: %d/%d, len: %d, flags: %#x\n",
575*4882a593Smuzhiyun 			      i + 1, num, msgs[i].len, msgs[i].flags);
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 		if (msgs[i].flags & I2C_M_RD)
578*4882a593Smuzhiyun 			ret = zx_hdmi_i2c_read(hdmi, &msgs[i]);
579*4882a593Smuzhiyun 		else
580*4882a593Smuzhiyun 			ret = zx_hdmi_i2c_write(hdmi, &msgs[i]);
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 		if (ret < 0)
583*4882a593Smuzhiyun 			break;
584*4882a593Smuzhiyun 	}
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	if (!ret)
587*4882a593Smuzhiyun 		ret = num;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	/* Disable DDC master access */
590*4882a593Smuzhiyun 	hdmi_writeb_mask(hdmi, TPI_DDC_MASTER_EN, HW_DDC_MASTER, 0);
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	mutex_unlock(&ddc->lock);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	return ret;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun 
zx_hdmi_i2c_func(struct i2c_adapter * adapter)597*4882a593Smuzhiyun static u32 zx_hdmi_i2c_func(struct i2c_adapter *adapter)
598*4882a593Smuzhiyun {
599*4882a593Smuzhiyun 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun static const struct i2c_algorithm zx_hdmi_algorithm = {
603*4882a593Smuzhiyun 	.master_xfer	= zx_hdmi_i2c_xfer,
604*4882a593Smuzhiyun 	.functionality	= zx_hdmi_i2c_func,
605*4882a593Smuzhiyun };
606*4882a593Smuzhiyun 
zx_hdmi_ddc_register(struct zx_hdmi * hdmi)607*4882a593Smuzhiyun static int zx_hdmi_ddc_register(struct zx_hdmi *hdmi)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun 	struct i2c_adapter *adap;
610*4882a593Smuzhiyun 	struct zx_hdmi_i2c *ddc;
611*4882a593Smuzhiyun 	int ret;
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
614*4882a593Smuzhiyun 	if (!ddc)
615*4882a593Smuzhiyun 		return -ENOMEM;
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	hdmi->ddc = ddc;
618*4882a593Smuzhiyun 	mutex_init(&ddc->lock);
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	adap = &ddc->adap;
621*4882a593Smuzhiyun 	adap->owner = THIS_MODULE;
622*4882a593Smuzhiyun 	adap->class = I2C_CLASS_DDC;
623*4882a593Smuzhiyun 	adap->dev.parent = hdmi->dev;
624*4882a593Smuzhiyun 	adap->algo = &zx_hdmi_algorithm;
625*4882a593Smuzhiyun 	snprintf(adap->name, sizeof(adap->name), "zx hdmi i2c");
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	ret = i2c_add_adapter(adap);
628*4882a593Smuzhiyun 	if (ret) {
629*4882a593Smuzhiyun 		DRM_DEV_ERROR(hdmi->dev, "failed to add I2C adapter: %d\n",
630*4882a593Smuzhiyun 			      ret);
631*4882a593Smuzhiyun 		return ret;
632*4882a593Smuzhiyun 	}
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	i2c_set_adapdata(adap, hdmi);
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	return 0;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun 
zx_hdmi_bind(struct device * dev,struct device * master,void * data)639*4882a593Smuzhiyun static int zx_hdmi_bind(struct device *dev, struct device *master, void *data)
640*4882a593Smuzhiyun {
641*4882a593Smuzhiyun 	struct platform_device *pdev = to_platform_device(dev);
642*4882a593Smuzhiyun 	struct drm_device *drm = data;
643*4882a593Smuzhiyun 	struct resource *res;
644*4882a593Smuzhiyun 	struct zx_hdmi *hdmi;
645*4882a593Smuzhiyun 	int irq;
646*4882a593Smuzhiyun 	int ret;
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
649*4882a593Smuzhiyun 	if (!hdmi)
650*4882a593Smuzhiyun 		return -ENOMEM;
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	hdmi->dev = dev;
653*4882a593Smuzhiyun 	hdmi->drm = drm;
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	dev_set_drvdata(dev, hdmi);
656*4882a593Smuzhiyun 
657*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
658*4882a593Smuzhiyun 	hdmi->mmio = devm_ioremap_resource(dev, res);
659*4882a593Smuzhiyun 	if (IS_ERR(hdmi->mmio)) {
660*4882a593Smuzhiyun 		ret = PTR_ERR(hdmi->mmio);
661*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to remap hdmi region: %d\n", ret);
662*4882a593Smuzhiyun 		return ret;
663*4882a593Smuzhiyun 	}
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
666*4882a593Smuzhiyun 	if (irq < 0)
667*4882a593Smuzhiyun 		return irq;
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun 	hdmi->cec_clk = devm_clk_get(hdmi->dev, "osc_cec");
670*4882a593Smuzhiyun 	if (IS_ERR(hdmi->cec_clk)) {
671*4882a593Smuzhiyun 		ret = PTR_ERR(hdmi->cec_clk);
672*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to get cec_clk: %d\n", ret);
673*4882a593Smuzhiyun 		return ret;
674*4882a593Smuzhiyun 	}
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	hdmi->osc_clk = devm_clk_get(hdmi->dev, "osc_clk");
677*4882a593Smuzhiyun 	if (IS_ERR(hdmi->osc_clk)) {
678*4882a593Smuzhiyun 		ret = PTR_ERR(hdmi->osc_clk);
679*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to get osc_clk: %d\n", ret);
680*4882a593Smuzhiyun 		return ret;
681*4882a593Smuzhiyun 	}
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	hdmi->xclk = devm_clk_get(hdmi->dev, "xclk");
684*4882a593Smuzhiyun 	if (IS_ERR(hdmi->xclk)) {
685*4882a593Smuzhiyun 		ret = PTR_ERR(hdmi->xclk);
686*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to get xclk: %d\n", ret);
687*4882a593Smuzhiyun 		return ret;
688*4882a593Smuzhiyun 	}
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	ret = zx_hdmi_ddc_register(hdmi);
691*4882a593Smuzhiyun 	if (ret) {
692*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to register ddc: %d\n", ret);
693*4882a593Smuzhiyun 		return ret;
694*4882a593Smuzhiyun 	}
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 	ret = zx_hdmi_audio_register(hdmi);
697*4882a593Smuzhiyun 	if (ret) {
698*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to register audio: %d\n", ret);
699*4882a593Smuzhiyun 		return ret;
700*4882a593Smuzhiyun 	}
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun 	ret = zx_hdmi_register(drm, hdmi);
703*4882a593Smuzhiyun 	if (ret) {
704*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to register hdmi: %d\n", ret);
705*4882a593Smuzhiyun 		return ret;
706*4882a593Smuzhiyun 	}
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(dev, irq, zx_hdmi_irq_handler,
709*4882a593Smuzhiyun 					zx_hdmi_irq_thread, IRQF_SHARED,
710*4882a593Smuzhiyun 					dev_name(dev), hdmi);
711*4882a593Smuzhiyun 	if (ret) {
712*4882a593Smuzhiyun 		DRM_DEV_ERROR(dev, "failed to request threaded irq: %d\n", ret);
713*4882a593Smuzhiyun 		return ret;
714*4882a593Smuzhiyun 	}
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	return 0;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun 
zx_hdmi_unbind(struct device * dev,struct device * master,void * data)719*4882a593Smuzhiyun static void zx_hdmi_unbind(struct device *dev, struct device *master,
720*4882a593Smuzhiyun 			   void *data)
721*4882a593Smuzhiyun {
722*4882a593Smuzhiyun 	struct zx_hdmi *hdmi = dev_get_drvdata(dev);
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	hdmi->connector.funcs->destroy(&hdmi->connector);
725*4882a593Smuzhiyun 	hdmi->encoder.funcs->destroy(&hdmi->encoder);
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	if (hdmi->audio_pdev)
728*4882a593Smuzhiyun 		platform_device_unregister(hdmi->audio_pdev);
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun static const struct component_ops zx_hdmi_component_ops = {
732*4882a593Smuzhiyun 	.bind = zx_hdmi_bind,
733*4882a593Smuzhiyun 	.unbind = zx_hdmi_unbind,
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun 
zx_hdmi_probe(struct platform_device * pdev)736*4882a593Smuzhiyun static int zx_hdmi_probe(struct platform_device *pdev)
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun 	return component_add(&pdev->dev, &zx_hdmi_component_ops);
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun 
zx_hdmi_remove(struct platform_device * pdev)741*4882a593Smuzhiyun static int zx_hdmi_remove(struct platform_device *pdev)
742*4882a593Smuzhiyun {
743*4882a593Smuzhiyun 	component_del(&pdev->dev, &zx_hdmi_component_ops);
744*4882a593Smuzhiyun 	return 0;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun static const struct of_device_id zx_hdmi_of_match[] = {
748*4882a593Smuzhiyun 	{ .compatible = "zte,zx296718-hdmi", },
749*4882a593Smuzhiyun 	{ /* end */ },
750*4882a593Smuzhiyun };
751*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, zx_hdmi_of_match);
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun struct platform_driver zx_hdmi_driver = {
754*4882a593Smuzhiyun 	.probe = zx_hdmi_probe,
755*4882a593Smuzhiyun 	.remove = zx_hdmi_remove,
756*4882a593Smuzhiyun 	.driver	= {
757*4882a593Smuzhiyun 		.name = "zx-hdmi",
758*4882a593Smuzhiyun 		.of_match_table	= zx_hdmi_of_match,
759*4882a593Smuzhiyun 	},
760*4882a593Smuzhiyun };
761