xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/hdmi.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunQualcomm adreno/snapdragon hdmi output
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun- compatible: one of the following
5*4882a593Smuzhiyun   * "qcom,hdmi-tx-8996"
6*4882a593Smuzhiyun   * "qcom,hdmi-tx-8994"
7*4882a593Smuzhiyun   * "qcom,hdmi-tx-8084"
8*4882a593Smuzhiyun   * "qcom,hdmi-tx-8974"
9*4882a593Smuzhiyun   * "qcom,hdmi-tx-8660"
10*4882a593Smuzhiyun   * "qcom,hdmi-tx-8960"
11*4882a593Smuzhiyun- reg: Physical base address and length of the controller's registers
12*4882a593Smuzhiyun- reg-names: "core_physical"
13*4882a593Smuzhiyun- interrupts: The interrupt signal from the hdmi block.
14*4882a593Smuzhiyun- power-domains: Should be <&mmcc MDSS_GDSC>.
15*4882a593Smuzhiyun- clocks: device clocks
16*4882a593Smuzhiyun  See ../clocks/clock-bindings.txt for details.
17*4882a593Smuzhiyun- core-vdda-supply: phandle to supply regulator
18*4882a593Smuzhiyun- hdmi-mux-supply: phandle to mux regulator
19*4882a593Smuzhiyun- phys: the phandle for the HDMI PHY device
20*4882a593Smuzhiyun- phy-names: the name of the corresponding PHY device
21*4882a593Smuzhiyun
22*4882a593SmuzhiyunOptional properties:
23*4882a593Smuzhiyun- hpd-gpios: hpd pin
24*4882a593Smuzhiyun- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
25*4882a593Smuzhiyun- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
26*4882a593Smuzhiyun- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
27*4882a593Smuzhiyun- power-domains: reference to the power domain(s), if available.
28*4882a593Smuzhiyun- pinctrl-names: the pin control state names; should contain "default"
29*4882a593Smuzhiyun- pinctrl-0: the default pinctrl state (active)
30*4882a593Smuzhiyun- pinctrl-1: the "sleep" pinctrl state
31*4882a593Smuzhiyun
32*4882a593SmuzhiyunHDMI PHY:
33*4882a593SmuzhiyunRequired properties:
34*4882a593Smuzhiyun- compatible: Could be the following
35*4882a593Smuzhiyun  * "qcom,hdmi-phy-8660"
36*4882a593Smuzhiyun  * "qcom,hdmi-phy-8960"
37*4882a593Smuzhiyun  * "qcom,hdmi-phy-8974"
38*4882a593Smuzhiyun  * "qcom,hdmi-phy-8084"
39*4882a593Smuzhiyun  * "qcom,hdmi-phy-8996"
40*4882a593Smuzhiyun- #phy-cells: Number of cells in a PHY specifier; Should be 0.
41*4882a593Smuzhiyun- reg: Physical base address and length of the registers of the PHY sub blocks.
42*4882a593Smuzhiyun- reg-names: The names of register regions. The following regions are required:
43*4882a593Smuzhiyun  * "hdmi_phy"
44*4882a593Smuzhiyun  * "hdmi_pll"
45*4882a593Smuzhiyun  For HDMI PHY on msm8996, these additional register regions are required:
46*4882a593Smuzhiyun    * "hdmi_tx_l0"
47*4882a593Smuzhiyun    * "hdmi_tx_l1"
48*4882a593Smuzhiyun    * "hdmi_tx_l3"
49*4882a593Smuzhiyun    * "hdmi_tx_l4"
50*4882a593Smuzhiyun- power-domains: Should be <&mmcc MDSS_GDSC>.
51*4882a593Smuzhiyun- clocks: device clocks
52*4882a593Smuzhiyun  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
53*4882a593Smuzhiyun- core-vdda-supply: phandle to vdda regulator device node
54*4882a593Smuzhiyun
55*4882a593SmuzhiyunExample:
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun/ {
58*4882a593Smuzhiyun	...
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	hdmi: hdmi@4a00000 {
61*4882a593Smuzhiyun		compatible = "qcom,hdmi-tx-8960";
62*4882a593Smuzhiyun		reg-names = "core_physical";
63*4882a593Smuzhiyun		reg = <0x04a00000 0x2f0>;
64*4882a593Smuzhiyun		interrupts = <GIC_SPI 79 0>;
65*4882a593Smuzhiyun		power-domains = <&mmcc MDSS_GDSC>;
66*4882a593Smuzhiyun		clock-names =
67*4882a593Smuzhiyun		    "core",
68*4882a593Smuzhiyun		    "master_iface",
69*4882a593Smuzhiyun		    "slave_iface";
70*4882a593Smuzhiyun		clocks =
71*4882a593Smuzhiyun		    <&mmcc HDMI_APP_CLK>,
72*4882a593Smuzhiyun		    <&mmcc HDMI_M_AHB_CLK>,
73*4882a593Smuzhiyun		    <&mmcc HDMI_S_AHB_CLK>;
74*4882a593Smuzhiyun		qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
75*4882a593Smuzhiyun		qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
76*4882a593Smuzhiyun		qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
77*4882a593Smuzhiyun		core-vdda-supply = <&pm8921_hdmi_mvs>;
78*4882a593Smuzhiyun		hdmi-mux-supply = <&ext_3p3v>;
79*4882a593Smuzhiyun		pinctrl-names = "default", "sleep";
80*4882a593Smuzhiyun		pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;
81*4882a593Smuzhiyun		pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun		phys = <&hdmi_phy>;
84*4882a593Smuzhiyun		phy-names = "hdmi_phy";
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	hdmi_phy: phy@4a00400 {
88*4882a593Smuzhiyun		compatible = "qcom,hdmi-phy-8960";
89*4882a593Smuzhiyun		reg-names = "hdmi_phy",
90*4882a593Smuzhiyun			    "hdmi_pll";
91*4882a593Smuzhiyun		reg = <0x4a00400 0x60>,
92*4882a593Smuzhiyun		      <0x4a00500 0x100>;
93*4882a593Smuzhiyun		#phy-cells = <0>;
94*4882a593Smuzhiyun		power-domains = <&mmcc MDSS_GDSC>;
95*4882a593Smuzhiyun		clock-names = "slave_iface";
96*4882a593Smuzhiyun		clocks = <&mmcc HDMI_S_AHB_CLK>;
97*4882a593Smuzhiyun		core-vdda-supply = <&pm8921_hdmi_mvs>;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun};
100