1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/* This include file covers the common peripherals and configuration between 4*4882a593Smuzhiyun * bcm2835, bcm2836 and bcm2837 implementations. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun interrupt-parent = <&intc>; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun soc { 11*4882a593Smuzhiyun dma: dma@7e007000 { 12*4882a593Smuzhiyun compatible = "brcm,bcm2835-dma"; 13*4882a593Smuzhiyun reg = <0x7e007000 0xf00>; 14*4882a593Smuzhiyun interrupts = <1 16>, 15*4882a593Smuzhiyun <1 17>, 16*4882a593Smuzhiyun <1 18>, 17*4882a593Smuzhiyun <1 19>, 18*4882a593Smuzhiyun <1 20>, 19*4882a593Smuzhiyun <1 21>, 20*4882a593Smuzhiyun <1 22>, 21*4882a593Smuzhiyun <1 23>, 22*4882a593Smuzhiyun <1 24>, 23*4882a593Smuzhiyun <1 25>, 24*4882a593Smuzhiyun <1 26>, 25*4882a593Smuzhiyun /* dma channel 11-14 share one irq */ 26*4882a593Smuzhiyun <1 27>, 27*4882a593Smuzhiyun <1 27>, 28*4882a593Smuzhiyun <1 27>, 29*4882a593Smuzhiyun <1 27>, 30*4882a593Smuzhiyun /* unused shared irq for all channels */ 31*4882a593Smuzhiyun <1 28>; 32*4882a593Smuzhiyun interrupt-names = "dma0", 33*4882a593Smuzhiyun "dma1", 34*4882a593Smuzhiyun "dma2", 35*4882a593Smuzhiyun "dma3", 36*4882a593Smuzhiyun "dma4", 37*4882a593Smuzhiyun "dma5", 38*4882a593Smuzhiyun "dma6", 39*4882a593Smuzhiyun "dma7", 40*4882a593Smuzhiyun "dma8", 41*4882a593Smuzhiyun "dma9", 42*4882a593Smuzhiyun "dma10", 43*4882a593Smuzhiyun "dma11", 44*4882a593Smuzhiyun "dma12", 45*4882a593Smuzhiyun "dma13", 46*4882a593Smuzhiyun "dma14", 47*4882a593Smuzhiyun "dma-shared-all"; 48*4882a593Smuzhiyun #dma-cells = <1>; 49*4882a593Smuzhiyun brcm,dma-channel-mask = <0x7f35>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun intc: interrupt-controller@7e00b200 { 53*4882a593Smuzhiyun compatible = "brcm,bcm2835-armctrl-ic"; 54*4882a593Smuzhiyun reg = <0x7e00b200 0x200>; 55*4882a593Smuzhiyun interrupt-controller; 56*4882a593Smuzhiyun #interrupt-cells = <2>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun pm: watchdog@7e100000 { 60*4882a593Smuzhiyun compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 61*4882a593Smuzhiyun #power-domain-cells = <1>; 62*4882a593Smuzhiyun #reset-cells = <1>; 63*4882a593Smuzhiyun reg = <0x7e100000 0x114>, 64*4882a593Smuzhiyun <0x7e00a000 0x24>; 65*4882a593Smuzhiyun clocks = <&clocks BCM2835_CLOCK_V3D>, 66*4882a593Smuzhiyun <&clocks BCM2835_CLOCK_PERI_IMAGE>, 67*4882a593Smuzhiyun <&clocks BCM2835_CLOCK_H264>, 68*4882a593Smuzhiyun <&clocks BCM2835_CLOCK_ISP>; 69*4882a593Smuzhiyun clock-names = "v3d", "peri_image", "h264", "isp"; 70*4882a593Smuzhiyun system-power-controller; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun rng@7e104000 { 74*4882a593Smuzhiyun compatible = "brcm,bcm2835-rng"; 75*4882a593Smuzhiyun reg = <0x7e104000 0x10>; 76*4882a593Smuzhiyun interrupts = <2 29>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun pixelvalve@7e206000 { 80*4882a593Smuzhiyun compatible = "brcm,bcm2835-pixelvalve0"; 81*4882a593Smuzhiyun reg = <0x7e206000 0x100>; 82*4882a593Smuzhiyun interrupts = <2 13>; /* pwa0 */ 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun pixelvalve@7e207000 { 86*4882a593Smuzhiyun compatible = "brcm,bcm2835-pixelvalve1"; 87*4882a593Smuzhiyun reg = <0x7e207000 0x100>; 88*4882a593Smuzhiyun interrupts = <2 14>; /* pwa1 */ 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun thermal: thermal@7e212000 { 92*4882a593Smuzhiyun compatible = "brcm,bcm2835-thermal"; 93*4882a593Smuzhiyun reg = <0x7e212000 0x8>; 94*4882a593Smuzhiyun clocks = <&clocks BCM2835_CLOCK_TSENS>; 95*4882a593Smuzhiyun #thermal-sensor-cells = <0>; 96*4882a593Smuzhiyun status = "disabled"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun i2c2: i2c@7e805000 { 100*4882a593Smuzhiyun compatible = "brcm,bcm2835-i2c"; 101*4882a593Smuzhiyun reg = <0x7e805000 0x1000>; 102*4882a593Smuzhiyun interrupts = <2 21>; 103*4882a593Smuzhiyun clocks = <&clocks BCM2835_CLOCK_VPU>; 104*4882a593Smuzhiyun #address-cells = <1>; 105*4882a593Smuzhiyun #size-cells = <0>; 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun pixelvalve@7e807000 { 110*4882a593Smuzhiyun compatible = "brcm,bcm2835-pixelvalve2"; 111*4882a593Smuzhiyun reg = <0x7e807000 0x100>; 112*4882a593Smuzhiyun interrupts = <2 10>; /* pixelvalve */ 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun hdmi: hdmi@7e902000 { 116*4882a593Smuzhiyun compatible = "brcm,bcm2835-hdmi"; 117*4882a593Smuzhiyun reg = <0x7e902000 0x600>, 118*4882a593Smuzhiyun <0x7e808000 0x100>; 119*4882a593Smuzhiyun interrupts = <2 8>, <2 9>; 120*4882a593Smuzhiyun ddc = <&i2c2>; 121*4882a593Smuzhiyun clocks = <&clocks BCM2835_PLLH_PIX>, 122*4882a593Smuzhiyun <&clocks BCM2835_CLOCK_HSM>; 123*4882a593Smuzhiyun clock-names = "pixel", "hdmi"; 124*4882a593Smuzhiyun dmas = <&dma 17>; 125*4882a593Smuzhiyun dma-names = "audio-rx"; 126*4882a593Smuzhiyun status = "disabled"; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun v3d: v3d@7ec00000 { 130*4882a593Smuzhiyun compatible = "brcm,bcm2835-v3d"; 131*4882a593Smuzhiyun reg = <0x7ec00000 0x1000>; 132*4882a593Smuzhiyun interrupts = <1 10>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun vc4: gpu { 136*4882a593Smuzhiyun compatible = "brcm,bcm2835-vc4"; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun&cpu_thermal { 142*4882a593Smuzhiyun thermal-sensors = <&thermal>; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&gpio { 146*4882a593Smuzhiyun i2c_slave_gpio18: i2c_slave_gpio18 { 147*4882a593Smuzhiyun brcm,pins = <18 19 20 21>; 148*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT3>; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun jtag_gpio4: jtag_gpio4 { 152*4882a593Smuzhiyun brcm,pins = <4 5 6 12 13>; 153*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT5>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun pwm0_gpio12: pwm0_gpio12 { 157*4882a593Smuzhiyun brcm,pins = <12>; 158*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT0>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun pwm0_gpio18: pwm0_gpio18 { 161*4882a593Smuzhiyun brcm,pins = <18>; 162*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT5>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun pwm0_gpio40: pwm0_gpio40 { 165*4882a593Smuzhiyun brcm,pins = <40>; 166*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT0>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun pwm1_gpio13: pwm1_gpio13 { 169*4882a593Smuzhiyun brcm,pins = <13>; 170*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT0>; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun pwm1_gpio19: pwm1_gpio19 { 173*4882a593Smuzhiyun brcm,pins = <19>; 174*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT5>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun pwm1_gpio41: pwm1_gpio41 { 177*4882a593Smuzhiyun brcm,pins = <41>; 178*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT0>; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun pwm1_gpio45: pwm1_gpio45 { 181*4882a593Smuzhiyun brcm,pins = <45>; 182*4882a593Smuzhiyun brcm,function = <BCM2835_FSEL_ALT0>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&i2s { 187*4882a593Smuzhiyun dmas = <&dma 2>, <&dma 3>; 188*4882a593Smuzhiyun dma-names = "tx", "rx"; 189*4882a593Smuzhiyun}; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun&sdhost { 192*4882a593Smuzhiyun dmas = <&dma 13>; 193*4882a593Smuzhiyun dma-names = "rx-tx"; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&spi { 197*4882a593Smuzhiyun dmas = <&dma 6>, <&dma 7>; 198*4882a593Smuzhiyun dma-names = "tx", "rx"; 199*4882a593Smuzhiyun}; 200