1*4882a593SmuzhiyunFreescale i.MX6 DWC HDMI TX Encoder 2*4882a593Smuzhiyun=================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP 5*4882a593Smuzhiyunwith a companion PHY IP. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThese DT bindings follow the Synopsys DWC HDMI TX bindings defined in 8*4882a593SmuzhiyunDocumentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the 9*4882a593Smuzhiyunfollowing device-specific properties. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi". 15*4882a593Smuzhiyun- reg: See dw_hdmi.txt. 16*4882a593Smuzhiyun- interrupts: HDMI interrupt number 17*4882a593Smuzhiyun- clocks: See dw_hdmi.txt. 18*4882a593Smuzhiyun- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt. 19*4882a593Smuzhiyun- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports, 20*4882a593Smuzhiyun numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer. 21*4882a593Smuzhiyun Each port shall have a single endpoint. 22*4882a593Smuzhiyun- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI 23*4882a593Smuzhiyun multiplexer control register. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunOptional properties 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master 28*4882a593Smuzhiyun or the functionally-reduced I2C master contained in the DWC HDMI. When 29*4882a593Smuzhiyun connected to a system I2C master this property contains a phandle to that 30*4882a593Smuzhiyun I2C master controller. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun gpr: iomuxc-gpr@20e0000 { 36*4882a593Smuzhiyun /* ... */ 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun hdmi: hdmi@120000 { 40*4882a593Smuzhiyun #address-cells = <1>; 41*4882a593Smuzhiyun #size-cells = <0>; 42*4882a593Smuzhiyun compatible = "fsl,imx6q-hdmi"; 43*4882a593Smuzhiyun reg = <0x00120000 0x9000>; 44*4882a593Smuzhiyun interrupts = <0 115 0x04>; 45*4882a593Smuzhiyun gpr = <&gpr>; 46*4882a593Smuzhiyun clocks = <&clks 123>, <&clks 124>; 47*4882a593Smuzhiyun clock-names = "iahb", "isfr"; 48*4882a593Smuzhiyun ddc-i2c-bus = <&i2c2>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun port@0 { 51*4882a593Smuzhiyun reg = <0>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun hdmi_mux_0: endpoint { 54*4882a593Smuzhiyun remote-endpoint = <&ipu1_di0_hdmi>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun port@1 { 59*4882a593Smuzhiyun reg = <1>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun hdmi_mux_1: endpoint { 62*4882a593Smuzhiyun remote-endpoint = <&ipu1_di1_hdmi>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66